gic_v3.hh revision 13756:12aa26df8c2f 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_H__
32#define __DEV_ARM_GICV3_H__
33
34#include "dev/arm/base_gic.hh"
35#include "params/Gicv3.hh"
36
37class Gicv3CPUInterface;
38class Gicv3Distributor;
39class Gicv3Redistributor;
40
41class Gicv3 : public BaseGic
42{
43  protected:
44
45    typedef Gicv3Params Params;
46    Gicv3Distributor * distributor;
47    std::vector<Gicv3Redistributor *> redistributors;
48    std::vector<Gicv3CPUInterface *> cpuInterfaces;
49    AddrRange distRange;
50    AddrRange redistRange;
51    AddrRangeList addrRanges;
52
53  public:
54
55    // Special interrupt IDs, as per SPEC 2.2.1 section
56    static const int INTID_SECURE = 1020;
57    static const int INTID_NONSECURE = 1021;
58    static const int INTID_SPURIOUS = 1023;
59
60    // Number of Software Generated Interrupts
61    static const int SGI_MAX = 16;
62    // Number of Private Peripheral Interrupts
63    static const int PPI_MAX = 16;
64
65    // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
66    typedef enum {
67        INT_INACTIVE,
68        INT_PENDING,
69        INT_ACTIVE,
70        INT_ACTIVE_PENDING,
71    } IntStatus;
72
73    // Interrupt groups, as per SPEC section 4.6
74    typedef enum {
75        G0S,
76        G1S,
77        G1NS,
78    } GroupId;
79
80    typedef enum {
81        INT_LEVEL_SENSITIVE,
82        INT_EDGE_TRIGGERED,
83    } IntTriggerType;
84
85  protected:
86
87    void clearInt(uint32_t int_id) override;
88    void clearPPInt(uint32_t int_id, uint32_t cpu) override;
89
90    inline AddrRangeList
91    getAddrRanges() const override
92    {
93        return addrRanges;
94    }
95
96    void init() override;
97    void initState() override;
98
99    const Params *
100    params() const
101    {
102        return dynamic_cast<const Params *>(_params);
103    }
104
105    Tick read(PacketPtr pkt) override;
106    void reset();
107    void sendInt(uint32_t int_id) override;
108    void sendPPInt(uint32_t int_id, uint32_t cpu) override;
109    void serialize(CheckpointOut & cp) const override;
110    void unserialize(CheckpointIn & cp) override;
111    Tick write(PacketPtr pkt) override;
112
113  public:
114
115    Gicv3(const Params * p);
116    void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
117
118    inline Gicv3CPUInterface *
119    getCPUInterface(int cpu_id) const
120    {
121        assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
122        return cpuInterfaces[cpu_id];
123    }
124
125    inline Gicv3Distributor *
126    getDistributor() const
127    {
128        return distributor;
129    }
130
131    inline Gicv3Redistributor *
132    getRedistributor(ContextID context_id) const
133    {
134        assert(context_id < redistributors.size() and
135               redistributors[context_id]);
136        return redistributors[context_id];
137    }
138
139    Gicv3Redistributor *
140    getRedistributorByAffinity(uint32_t affinity) const;
141    void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
142};
143
144#endif //__DEV_ARM_GICV3_H__
145