xref: /gem5/src/dev/arm/SConscript

# -*- mode:python -*-

# Copyright (c) 2009, 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi

Import('*')

if env['TARGET_ISA'] == 'arm':
    SimObject('AbstractNVM.py')
    SimObject('FlashDevice.py')
    SimObject('Gic.py')
    SimObject('RealView.py')
    SimObject('SMMUv3.py')
    SimObject('UFSHostDevice.py')
    SimObject('EnergyCtrl.py')
    SimObject('NoMali.py')
    SimObject('VirtIOMMIO.py')

    Source('a9scu.cc')
    Source('amba_device.cc')
    Source('amba_fake.cc')
    Source('base_gic.cc')
    Source('flash_device.cc')
    Source('generic_timer.cc')
    Source('gic_v2.cc')
    Source('gic_v2m.cc')
    Source('gic_v3.cc')
    Source('gic_v3_cpu_interface.cc')
    Source('gic_v3_distributor.cc')
    Source('gic_v3_redistributor.cc')
    Source('gic_v3_its.cc')
    Source('pl011.cc')
    Source('pl111.cc')
    Source('hdlcd.cc')
    Source('kmi.cc')
    Source('smmu_v3.cc');
    Source('smmu_v3_caches.cc');
    Source('smmu_v3_cmdexec.cc');
    Source('smmu_v3_events.cc');
    Source('smmu_v3_ports.cc');
    Source('smmu_v3_proc.cc');
    Source('smmu_v3_ptops.cc');
    Source('smmu_v3_slaveifc.cc');
    Source('smmu_v3_transl.cc');
    Source('timer_sp804.cc')
    Source('gpu_nomali.cc')
    Source('pci_host.cc')
    Source('rv_ctrl.cc')
    Source('realview.cc')
    Source('rtc_pl031.cc')
    Source('timer_cpulocal.cc')
    Source('timer_a9global.cc')
    Source('vgic.cc')
    Source('vio_mmio.cc')
    Source('ufs_device.cc')
    Source('energy_ctrl.cc')

    DebugFlag('AMBA')
    DebugFlag('FlashDevice')
    DebugFlag('HDLcd')
    DebugFlag('PL111')
    DebugFlag('GICV2M')
    DebugFlag('Pl050')
    DebugFlag('GIC')
    DebugFlag('ITS')
    DebugFlag('RVCTRL')
    DebugFlag('SMMUv3')
    DebugFlag('SMMUv3Hazard')
    DebugFlag('EnergyCtrl')
    DebugFlag('UFSHostDevice')
    DebugFlag('VGIC')
    DebugFlag('NoMali')