RealView.py revision 8524
1# Copyright (c) 2009 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Ide import * 47from Platform import Platform 48from Terminal import Terminal 49from Uart import Uart 50 51class AmbaDevice(BasicPioDevice): 52 type = 'AmbaDevice' 53 abstract = True 54 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 55 56class AmbaIntDevice(AmbaDevice): 57 type = 'AmbaIntDevice' 58 abstract = True 59 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 60 int_num = Param.UInt32("Interrupt number that connects to GIC") 61 int_delay = Param.Latency("100ns", 62 "Time between action and interrupt generation by device") 63 64class AmbaDmaDevice(DmaDevice): 65 type = 'AmbaDmaDevice' 66 abstract = True 67 pio_addr = Param.Addr("Address for AMBA slave interface") 68 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 69 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 70 int_num = Param.UInt32("Interrupt number that connects to GIC") 71 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 72 73class A9SCU(BasicPioDevice): 74 type = 'A9SCU' 75 76class RealViewCtrl(BasicPioDevice): 77 type = 'RealViewCtrl' 78 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 79 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 80 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 81 82class Gic(PioDevice): 83 type = 'Gic' 84 dist_addr = Param.Addr(0x1f001000, "Address for distributor") 85 cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 86 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 87 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 88 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 89 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 90 91class AmbaFake(AmbaDevice): 92 type = 'AmbaFake' 93 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 94 amba_id = 0; 95 96class Pl011(Uart): 97 type = 'Pl011' 98 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 99 int_num = Param.UInt32("Interrupt number that connects to GIC") 100 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 101 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 102 103class Sp804(AmbaDevice): 104 type = 'Sp804' 105 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 106 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 107 clock0 = Param.Clock('1MHz', "Clock speed of the input") 108 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 109 clock1 = Param.Clock('1MHz', "Clock speed of the input") 110 amba_id = 0x00141804 111 112class CpuLocalTimer(BasicPioDevice): 113 type = 'CpuLocalTimer' 114 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 115 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 116 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 117 clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 118 119class Pl050(AmbaIntDevice): 120 type = 'Pl050' 121 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 122 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 123 int_delay = '1us' 124 amba_id = 0x00141050 125 126class Pl111(AmbaDmaDevice): 127 type = 'Pl111' 128 clock = Param.Clock('24MHz', "Clock speed of the input") 129 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 130 amba_id = 0x00141111 131 132class RealView(Platform): 133 type = 'RealView' 134 system = Param.System(Parent.any, "system") 135 136# Reference for memory map and interrupt number 137# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 138# Chapter 4: Programmer's Reference 139class RealViewPBX(RealView): 140 uart = Pl011(pio_addr=0x10009000, int_num=44) 141 realview_io = RealViewCtrl(pio_addr=0x10000000) 142 gic = Gic() 143 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 144 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 145 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 146 clcd = Pl111(pio_addr=0x10020000, int_num=55) 147 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 148 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 149 a9scu = A9SCU(pio_addr=0x1f000000) 150 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0, 151 io_shift = 1, ctrl_offset = 2, Command = 0x1, 152 BAR0 = 0x18000000, BAR0Size = '16B', 153 BAR1 = 0x18000100, BAR1Size = '1B', 154 BAR0LegacyIO = True, BAR1LegacyIO = True) 155 156 157 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 158 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 159 fake_mem=True) 160 dmac_fake = AmbaFake(pio_addr=0x10030000) 161 uart1_fake = AmbaFake(pio_addr=0x1000a000) 162 uart2_fake = AmbaFake(pio_addr=0x1000b000) 163 uart3_fake = AmbaFake(pio_addr=0x1000c000) 164 smc_fake = AmbaFake(pio_addr=0x100e1000) 165 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 166 watchdog_fake = AmbaFake(pio_addr=0x10010000) 167 gpio0_fake = AmbaFake(pio_addr=0x10013000) 168 gpio1_fake = AmbaFake(pio_addr=0x10014000) 169 gpio2_fake = AmbaFake(pio_addr=0x10015000) 170 ssp_fake = AmbaFake(pio_addr=0x1000d000) 171 sci_fake = AmbaFake(pio_addr=0x1000e000) 172 aaci_fake = AmbaFake(pio_addr=0x10004000) 173 mmc_fake = AmbaFake(pio_addr=0x10005000) 174 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 175 176 177 # Attach I/O devices that are on chip 178 def attachOnChipIO(self, bus): 179 self.gic.pio = bus.port 180 self.l2x0_fake.pio = bus.port 181 self.a9scu.pio = bus.port 182 self.local_cpu_timer.pio = bus.port 183 184 # Attach I/O devices to specified bus object. Can't do this 185 # earlier, since the bus object itself is typically defined at the 186 # System level. 187 def attachIO(self, bus): 188 self.uart.pio = bus.port 189 self.realview_io.pio = bus.port 190 self.timer0.pio = bus.port 191 self.timer1.pio = bus.port 192 self.clcd.pio = bus.port 193 self.kmi0.pio = bus.port 194 self.kmi1.pio = bus.port 195 self.cf_ctrl.pio = bus.port 196 self.dmac_fake.pio = bus.port 197 self.uart1_fake.pio = bus.port 198 self.uart2_fake.pio = bus.port 199 self.uart3_fake.pio = bus.port 200 self.smc_fake.pio = bus.port 201 self.sp810_fake.pio = bus.port 202 self.watchdog_fake.pio = bus.port 203 self.gpio0_fake.pio = bus.port 204 self.gpio1_fake.pio = bus.port 205 self.gpio2_fake.pio = bus.port 206 self.ssp_fake.pio = bus.port 207 self.sci_fake.pio = bus.port 208 self.aaci_fake.pio = bus.port 209 self.mmc_fake.pio = bus.port 210 self.rtc_fake.pio = bus.port 211 self.flash_fake.pio = bus.port 212 213# Reference for memory map and interrupt number 214# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 215# Chapter 4: Programmer's Reference 216class RealViewEB(RealView): 217 uart = Pl011(pio_addr=0x10009000, int_num=44) 218 realview_io = RealViewCtrl(pio_addr=0x10000000) 219 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 220 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 221 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 222 clcd = Pl111(pio_addr=0x10020000, int_num=23) 223 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 224 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 225 226 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 227 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 228 fake_mem=True) 229 dmac_fake = AmbaFake(pio_addr=0x10030000) 230 uart1_fake = AmbaFake(pio_addr=0x1000a000) 231 uart2_fake = AmbaFake(pio_addr=0x1000b000) 232 uart3_fake = AmbaFake(pio_addr=0x1000c000) 233 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 234 smc_fake = AmbaFake(pio_addr=0x100e1000) 235 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 236 watchdog_fake = AmbaFake(pio_addr=0x10010000) 237 gpio0_fake = AmbaFake(pio_addr=0x10013000) 238 gpio1_fake = AmbaFake(pio_addr=0x10014000) 239 gpio2_fake = AmbaFake(pio_addr=0x10015000) 240 ssp_fake = AmbaFake(pio_addr=0x1000d000) 241 sci_fake = AmbaFake(pio_addr=0x1000e000) 242 aaci_fake = AmbaFake(pio_addr=0x10004000) 243 mmc_fake = AmbaFake(pio_addr=0x10005000) 244 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 245 246 247 248 # Attach I/O devices that are on chip 249 def attachOnChipIO(self, bus): 250 self.gic.pio = bus.port 251 self.l2x0_fake.pio = bus.port 252 253 # Attach I/O devices to specified bus object. Can't do this 254 # earlier, since the bus object itself is typically defined at the 255 # System level. 256 def attachIO(self, bus): 257 self.uart.pio = bus.port 258 self.realview_io.pio = bus.port 259 self.timer0.pio = bus.port 260 self.timer1.pio = bus.port 261 self.clcd.pio = bus.port 262 self.kmi0.pio = bus.port 263 self.kmi1.pio = bus.port 264 self.dmac_fake.pio = bus.port 265 self.uart1_fake.pio = bus.port 266 self.uart2_fake.pio = bus.port 267 self.uart3_fake.pio = bus.port 268 self.smc_fake.pio = bus.port 269 self.sp810_fake.pio = bus.port 270 self.watchdog_fake.pio = bus.port 271 self.gpio0_fake.pio = bus.port 272 self.gpio1_fake.pio = bus.port 273 self.gpio2_fake.pio = bus.port 274 self.ssp_fake.pio = bus.port 275 self.sci_fake.pio = bus.port 276 self.aaci_fake.pio = bus.port 277 self.mmc_fake.pio = bus.port 278 self.rtc_fake.pio = bus.port 279 self.flash_fake.pio = bus.port 280 self.smcreg_fake.pio = bus.port 281 282class VExpress(RealView): 283 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 284 uart = Pl011(pio_addr=0xFF009000, int_num=121) 285 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 286 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 287 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 288 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 289 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 290 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 291 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 292 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 293 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 294 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 295 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 296 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 297 a9scu = A9SCU(pio_addr=0xE0200000) 298 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0, 299 io_shift = 2, ctrl_offset = 2, Command = 0x1, 300 BAR0 = 0xFF01A000, BAR0Size = '256B', 301 BAR1 = 0xFF01A100, BAR1Size = '4096B', 302 BAR0LegacyIO = True, BAR1LegacyIO = True) 303 304 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 305 dmac_fake = AmbaFake(pio_addr=0xE0020000) 306 uart1_fake = AmbaFake(pio_addr=0xE000A000) 307 uart2_fake = AmbaFake(pio_addr=0xE000B000) 308 uart3_fake = AmbaFake(pio_addr=0xE000C000) 309 smc_fake = AmbaFake(pio_addr=0xEC000000) 310 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 311 watchdog_fake = AmbaFake(pio_addr=0xE0010000) 312 aaci_fake = AmbaFake(pio_addr=0xFF004000) 313 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 314 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 315 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 316 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 317 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 318 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 319 320 321 # Attach I/O devices that are on chip 322 def attachOnChipIO(self, bus): 323 self.gic.pio = bus.port 324 self.a9scu.pio = bus.port 325 326 # Attach I/O devices to specified bus object. Can't do this 327 # earlier, since the bus object itself is typically defined at the 328 # System level. 329 def attachIO(self, bus): 330 self.elba_uart.pio = bus.port 331 self.uart.pio = bus.port 332 self.realview_io.pio = bus.port 333 self.local_cpu_timer.pio = bus.port 334 self.v2m_timer0.pio = bus.port 335 self.v2m_timer1.pio = bus.port 336 self.elba_timer0.pio = bus.port 337 self.elba_timer1.pio = bus.port 338 self.clcd.pio = bus.port 339 self.kmi0.pio = bus.port 340 self.kmi1.pio = bus.port 341 self.elba_kmi0.pio = bus.port 342 self.elba_kmi1.pio = bus.port 343 self.cf_ctrl.pio = bus.port 344 self.l2x0_fake.pio = bus.port 345 self.dmac_fake.pio = bus.port 346 self.uart1_fake.pio = bus.port 347 self.uart2_fake.pio = bus.port 348 self.uart3_fake.pio = bus.port 349 self.smc_fake.pio = bus.port 350 self.sp810_fake.pio = bus.port 351 self.watchdog_fake.pio = bus.port 352 self.aaci_fake.pio = bus.port 353 self.elba_aaci_fake.pio = bus.port 354 self.mmc_fake.pio = bus.port 355 self.rtc_fake.pio = bus.port 356 self.spsc_fake.pio = bus.port 357 self.lan_fake.pio = bus.port 358 self.usb_fake.pio = bus.port 359 360