RealView.py revision 12733
11689SN/A# Copyright (c) 2009-2018 ARM Limited 22316SN/A# All rights reserved. 31689SN/A# 41689SN/A# The license below extends only to copyright in the software and shall 51689SN/A# not be construed as granting a license to any other intellectual 61689SN/A# property including but not limited to intellectual property relating 71689SN/A# to a hardware implementation of the functionality of the software 81689SN/A# licensed hereunder. You may use the software subject to the license 91689SN/A# terms below provided that you ensure that this notice is replicated 101689SN/A# unmodified and in its entirety in all distributions of the software, 111689SN/A# modified or unmodified, in source code or in binary form. 121689SN/A# 131689SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 141689SN/A# All rights reserved. 151689SN/A# 161689SN/A# Redistribution and use in source and binary forms, with or without 171689SN/A# modification, are permitted provided that the following conditions are 181689SN/A# met: redistributions of source code must retain the above copyright 191689SN/A# notice, this list of conditions and the following disclaimer; 201689SN/A# redistributions in binary form must reproduce the above copyright 211689SN/A# notice, this list of conditions and the following disclaimer in the 221689SN/A# documentation and/or other materials provided with the distribution; 231689SN/A# neither the name of the copyright holders nor the names of its 241689SN/A# contributors may be used to endorse or promote products derived from 251689SN/A# this software without specific prior written permission. 261689SN/A# 272665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292965Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 301689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 311689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322733Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332733Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342733Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352292SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362329SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372292SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383577Sgblack@eecs.umich.edu# 395953Ssaidi@eecs.umich.edu# Authors: Ali Saidi 402292SN/A# Gabe Black 411060SN/A# William Wang 422292SN/A# Glenn Bergmans 431717SN/A 442292SN/Afrom m5.defines import buildEnv 452292SN/Afrom m5.params import * 462790Sktlim@umich.edufrom m5.proxy import * 472790Sktlim@umich.edufrom m5.util.fdthelper import * 482790Sktlim@umich.edufrom ClockDomain import ClockDomain 492790Sktlim@umich.edufrom VoltageDomain import VoltageDomain 505529Snate@binkert.orgfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 515529Snate@binkert.orgfrom PciHost import * 521061SN/Afrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 532292SN/Afrom Ide import * 542292SN/Afrom Platform import Platform 555606Snate@binkert.orgfrom Terminal import Terminal 561060SN/Afrom Uart import Uart 575769Snate@binkert.orgfrom SimpleMemory import SimpleMemory 581060SN/Afrom Gic import * 591060SN/Afrom EnergyCtrl import EnergyCtrl 601061SN/Afrom ClockedObject import ClockedObject 611060SN/Afrom ClockDomain import SrcClockDomain 622292SN/Afrom SubSystem import SubSystem 631062SN/Afrom Graphics import ImageFormat 642316SN/Afrom ClockedObject import ClockedObject 652316SN/Afrom PS2 import * 662292SN/A 672292SN/A# Platforms with KVM support should generally use in-kernel GIC 682292SN/A# emulation. Use a GIC model that automatically switches between 692292SN/A# gem5's GIC model and KVM's GIC model if KVM is available. 702292SN/Atry: 715336Shines@cs.fsu.edu from KvmGic import MuxingKvmGic 722292SN/A kvm_gicv2_class = MuxingKvmGic 734873Sstever@eecs.umich.eduexcept ImportError: 742292SN/A # KVM support wasn't compiled into gem5. Fallback to a 752292SN/A # software-only GIC. 762292SN/A kvm_gicv2_class = Pl390 775529Snate@binkert.org pass 784329Sktlim@umich.edu 794329Sktlim@umich.educlass AmbaPioDevice(BasicPioDevice): 802292SN/A type = 'AmbaPioDevice' 812292SN/A abstract = True 822292SN/A cxx_header = "dev/arm/amba_device.hh" 832292SN/A amba_id = Param.UInt32("ID of AMBA device for kernel detection") 842292SN/A 852292SN/Aclass AmbaIntDevice(AmbaPioDevice): 865529Snate@binkert.org type = 'AmbaIntDevice' 872843Sktlim@umich.edu abstract = True 882316SN/A cxx_header = "dev/arm/amba_device.hh" 892874Sktlim@umich.edu gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 902292SN/A int_num = Param.UInt32("Interrupt number that connects to GIC") 912292SN/A int_delay = Param.Latency("100ns", 922292SN/A "Time between action and interrupt generation by device") 932980Sgblack@eecs.umich.edu 942292SN/Aclass AmbaDmaDevice(DmaDevice): 952292SN/A type = 'AmbaDmaDevice' 962292SN/A abstract = True 972292SN/A cxx_header = "dev/arm/amba_device.hh" 982292SN/A pio_addr = Param.Addr("Address for AMBA slave interface") 992292SN/A pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 1002292SN/A gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1012292SN/A int_num = Param.UInt32("Interrupt number that connects to GIC") 1022292SN/A amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1034329Sktlim@umich.edu 1042292SN/Aclass A9SCU(BasicPioDevice): 1052292SN/A type = 'A9SCU' 1062292SN/A cxx_header = "dev/arm/a9scu.hh" 1072292SN/A 1082292SN/Aclass ArmPciIntRouting(Enum): vals = [ 1092292SN/A 'ARM_PCI_INT_STATIC', 1102292SN/A 'ARM_PCI_INT_DEV', 1112292SN/A 'ARM_PCI_INT_PIN', 1124329Sktlim@umich.edu ] 1132292SN/A 1142292SN/Aclass GenericArmPciHost(GenericPciHost): 1152292SN/A type = 'GenericArmPciHost' 1164329Sktlim@umich.edu cxx_header = "dev/arm/pci_host.hh" 1172292SN/A 1182292SN/A int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 1192292SN/A int_base = Param.Unsigned("PCI interrupt base") 1202292SN/A int_count = Param.Unsigned("Maximum number of interrupts used by this host") 1212292SN/A 1222292SN/A def generateDeviceTree(self, state): 1232292SN/A local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 1242292SN/A intterrupt_cells = 1 1254035Sktlim@umich.edu 1264035Sktlim@umich.edu node = FdtNode("pci") 1274035Sktlim@umich.edu 1282292SN/A if int(self.conf_device_bits) == 8: 1292680Sktlim@umich.edu node.appendCompatible("pci-host-cam-generic") 1304636Sgblack@eecs.umich.edu elif int(self.conf_device_bits) == 12: 1312292SN/A node.appendCompatible("pci-host-ecam-generic") 1323640Sktlim@umich.edu else: 1333640Sktlim@umich.edu m5.fatal("No compatibility string for the set conf_device_width") 1343640Sktlim@umich.edu 1352292SN/A node.append(FdtPropertyStrings("device_type", ["pci"])) 1362292SN/A 1372292SN/A # Cell sizes of child nodes/peripherals 1382292SN/A node.append(local_state.addrCellsProperty()) 1392292SN/A node.append(local_state.sizeCellsProperty()) 1402292SN/A node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 1412292SN/A # PCI address for CPU 1422292SN/A node.append(FdtPropertyWords("reg", 1432292SN/A state.addrCells(self.conf_base) + 1442292SN/A state.sizeCells(self.conf_size) )) 1452292SN/A 1462292SN/A # Ranges mapping 1472132SN/A # For now some of this is hard coded, because the PCI module does not 1482301SN/A # have a proper full understanding of the memory map, but adapting the 1491062SN/A # PCI module is beyond the scope of what I'm trying to do here. 1501062SN/A # Values are taken from the VExpress_GEM5_V1 platform. 1511062SN/A ranges = [] 1521062SN/A # Pio address range 1531062SN/A ranges += self.pciFdtAddr(space=1, addr=0) 1541062SN/A ranges += state.addrCells(self.pci_pio_base) 1551062SN/A ranges += local_state.sizeCells(0x10000) # Fixed size 1561062SN/A 1571062SN/A # AXI memory address range 1581062SN/A ranges += self.pciFdtAddr(space=2, addr=0) 1591062SN/A ranges += state.addrCells(0x40000000) # Fixed offset 1601062SN/A ranges += local_state.sizeCells(0x40000000) # Fixed size 1611062SN/A node.append(FdtPropertyWords("ranges", ranges)) 1621062SN/A 1631062SN/A if str(self.int_policy) == 'ARM_PCI_INT_DEV': 1641062SN/A int_phandle = state.phandle(self._parent.unproxy(self).gic) 1651062SN/A # Interrupt mapping 1661062SN/A interrupts = [] 1671062SN/A for i in range(int(self.int_count)): 1681062SN/A interrupts += self.pciFdtAddr(device=i, addr=0) + \ 1691062SN/A [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 1702292SN/A 1711062SN/A node.append(FdtPropertyWords("interrupt-map", interrupts)) 1721062SN/A 1731062SN/A int_count = int(self.int_count) 1741062SN/A if int_count & (int_count - 1): 1751062SN/A fatal("PCI interrupt count should be power of 2") 1762301SN/A 1772316SN/A intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 1782301SN/A node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 1792301SN/A else: 1802301SN/A m5.fatal("Unsupported PCI interrupt policy " + 1812301SN/A "for Device Tree generation") 1822301SN/A 1832301SN/A node.append(FdtProperty("dma-coherent")) 1842316SN/A 1852301SN/A yield node 1862301SN/A 1872301SN/Aclass RealViewCtrl(BasicPioDevice): 1882301SN/A type = 'RealViewCtrl' 1892301SN/A cxx_header = "dev/arm/rv_ctrl.hh" 1902301SN/A proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1912316SN/A proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1922301SN/A idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1932301SN/A 1942301SN/A def generateDeviceTree(self, state): 1952301SN/A node = FdtNode("sysreg@%x" % long(self.pio_addr)) 1962301SN/A node.appendCompatible("arm,vexpress-sysreg") 1972301SN/A node.append(FdtPropertyWords("reg", 1982316SN/A state.addrCells(self.pio_addr) + 1992301SN/A state.sizeCells(0x1000) )) 2002301SN/A node.append(FdtProperty("gpio-controller")) 2012301SN/A node.append(FdtPropertyWords("#gpio-cells", [2])) 2022301SN/A node.appendPhandle(self) 2032301SN/A 2042301SN/A yield node 2052316SN/A 2062301SN/Aclass RealViewOsc(ClockDomain): 2072301SN/A type = 'RealViewOsc' 2082301SN/A cxx_header = "dev/arm/rv_ctrl.hh" 2092301SN/A 2102301SN/A parent = Param.RealViewCtrl(Parent.any, "RealView controller") 2112301SN/A 2122316SN/A # TODO: We currently don't have the notion of a clock source, 2132301SN/A # which means we have to associate oscillators with a voltage 2142301SN/A # source. 2152301SN/A voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 2162301SN/A "Voltage domain") 2172301SN/A 2182301SN/A # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 2192316SN/A # the individual core/logic tile reference manuals for details 2202301SN/A # about the site/position/dcc/device allocation. 2212301SN/A site = Param.UInt8("Board Site") 2222301SN/A position = Param.UInt8("Position in device stack") 2232301SN/A dcc = Param.UInt8("Daughterboard Configuration Controller") 2242301SN/A device = Param.UInt8("Device ID") 2252301SN/A 2262316SN/A freq = Param.Clock("Default frequency") 2272301SN/A 2282301SN/A def generateDeviceTree(self, state): 2292301SN/A phandle = state.phandle(self) 2301062SN/A node = FdtNode("osc@" + format(long(phandle), 'x')) 2311062SN/A node.appendCompatible("arm,vexpress-osc") 2321062SN/A node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 2331062SN/A [0x1, int(self.device)])) 2342980Sgblack@eecs.umich.edu node.append(FdtPropertyWords("#clock-cells", [0])) 2352292SN/A freq = int(1.0/self.freq.value) # Values are stored as a clock period 2362292SN/A node.append(FdtPropertyWords("freq-range", [freq, freq])) 2372292SN/A node.append(FdtPropertyStrings("clock-output-names", 2382292SN/A ["oscclk" + str(phandle)])) 2392292SN/A node.appendPhandle(self) 2402292SN/A yield node 2412292SN/A 2421060SN/Aclass RealViewTemperatureSensor(SimObject): 2431060SN/A type = 'RealViewTemperatureSensor' 2441060SN/A cxx_header = "dev/arm/rv_ctrl.hh" 2451060SN/A 2461060SN/A parent = Param.RealViewCtrl(Parent.any, "RealView controller") 2471060SN/A 2481060SN/A system = Param.System(Parent.any, "system") 2491060SN/A 2501060SN/A # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 2511060SN/A # the individual core/logic tile reference manuals for details 2521061SN/A # about the site/position/dcc/device allocation. 2531060SN/A site = Param.UInt8("Board Site") 2542292SN/A position = Param.UInt8("Position in device stack") 2552292SN/A dcc = Param.UInt8("Daughterboard Configuration Controller") 2562292SN/A device = Param.UInt8("Device ID") 2572292SN/A 2582292SN/Aclass VExpressMCC(SubSystem): 2592292SN/A """ARM V2M-P1 Motherboard Configuration Controller 2602292SN/A 2612292SN/AThis subsystem describes a subset of the devices that sit behind the 2622292SN/Amotherboard configuration controller on the the ARM Motherboard 2632292SN/AExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 2642292SN/A """ 2651060SN/A 2661060SN/A class Osc(RealViewOsc): 2671060SN/A site, position, dcc = (0, 0, 0) 2681060SN/A 2691060SN/A class Temperature(RealViewTemperatureSensor): 2701060SN/A site, position, dcc = (0, 0, 0) 2711060SN/A 2721061SN/A osc_mcc = Osc(device=0, freq="50MHz") 2731060SN/A osc_clcd = Osc(device=1, freq="23.75MHz") 2742292SN/A osc_peripheral = Osc(device=2, freq="24MHz") 2751060SN/A osc_system_bus = Osc(device=4, freq="24MHz") 2761060SN/A 2771060SN/A # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 2781060SN/A temp_crtl = Temperature(device=0) 2791060SN/A 2801060SN/A def generateDeviceTree(self, state): 2811060SN/A node = FdtNode("mcc") 2821061SN/A node.appendCompatible("arm,vexpress,config-bus") 2831060SN/A node.append(FdtPropertyWords("arm,vexpress,site", [0])) 2842292SN/A 2852292SN/A for obj in self._children.values(): 2862292SN/A if issubclass(type(obj), SimObject): 2872292SN/A node.append(obj.generateDeviceTree(state)) 2882292SN/A 2892292SN/A io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 2902292SN/A node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 2912980Sgblack@eecs.umich.edu 2922292SN/A yield node 2932292SN/A 2942292SN/Aclass CoreTile2A15DCC(SubSystem): 2952292SN/A """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 2962292SN/A 2972292SN/AThis subsystem describes a subset of the devices that sit behind the 2982292SN/Adaughterboard configuration controller on a CoreTile Express A15x2. See 2992292SN/AARM DUI 0604E for details. 3002292SN/A """ 3012292SN/A 3022292SN/A class Osc(RealViewOsc): 3032292SN/A site, position, dcc = (1, 0, 0) 3042292SN/A 3052292SN/A # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 3062292SN/A osc_cpu = Osc(device=0, freq="60MHz") 3072292SN/A osc_hsbm = Osc(device=4, freq="40MHz") 3081060SN/A osc_pxl = Osc(device=5, freq="23.75MHz") 3091060SN/A osc_smb = Osc(device=6, freq="50MHz") 3101060SN/A osc_sys = Osc(device=7, freq="60MHz") 3111060SN/A osc_ddr = Osc(device=8, freq="40MHz") 3121061SN/A 3131060SN/A def generateDeviceTree(self, state): 3142292SN/A node = FdtNode("dcc") 3151060SN/A node.appendCompatible("arm,vexpress,config-bus") 3162292SN/A 3172292SN/A for obj in self._children.values(): 3181060SN/A if isinstance(obj, SimObject): 3192292SN/A node.append(obj.generateDeviceTree(state)) 3202292SN/A 3212292SN/A io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 3222292SN/A node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 3234035Sktlim@umich.edu 3241060SN/A yield node 3251060SN/A 3264329Sktlim@umich.educlass VGic(PioDevice): 3274329Sktlim@umich.edu type = 'VGic' 3284329Sktlim@umich.edu cxx_header = "dev/arm/vgic.hh" 3294329Sktlim@umich.edu gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3302292SN/A platform = Param.Platform(Parent.any, "Platform this device is part of.") 3315100Ssaidi@eecs.umich.edu vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 3321060SN/A hv_addr = Param.Addr(0, "Address for hv control") 3331060SN/A pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 3341061SN/A # The number of list registers is not currently configurable at runtime. 3352863Sktlim@umich.edu ppint = Param.UInt32("HV maintenance interrupt number") 3362843Sktlim@umich.edu 3371060SN/A def generateDeviceTree(self, state): 3382843Sktlim@umich.edu gic = self.gic.unproxy(self) 3392863Sktlim@umich.edu 3402863Sktlim@umich.edu node = FdtNode("interrupt-controller") 3412316SN/A node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 3422316SN/A "arm,cortex-a9-gic"]) 3432316SN/A node.append(FdtPropertyWords("#interrupt-cells", [3])) 3442316SN/A node.append(FdtPropertyWords("#address-cells", [0])) 3452843Sktlim@umich.edu node.append(FdtProperty("interrupt-controller")) 3462316SN/A 3472316SN/A regs = ( 3482843Sktlim@umich.edu state.addrCells(gic.dist_addr) + 3492307SN/A state.sizeCells(0x1000) + 3502307SN/A state.addrCells(gic.cpu_addr) + 3512307SN/A state.sizeCells(0x1000) + 3522307SN/A state.addrCells(self.hv_addr) + 3532307SN/A state.sizeCells(0x2000) + 3542843Sktlim@umich.edu state.addrCells(self.vcpu_addr) + 3552843Sktlim@umich.edu state.sizeCells(0x2000) ) 3562864Sktlim@umich.edu 3572843Sktlim@umich.edu node.append(FdtPropertyWords("reg", regs)) 3582843Sktlim@umich.edu node.append(FdtPropertyWords("interrupts", 3592843Sktlim@umich.edu [1, int(self.ppint)-16, 0xf04])) 3602843Sktlim@umich.edu 3612307SN/A node.appendPhandle(gic) 3622307SN/A 3632316SN/A yield node 3642307SN/A 3652307SN/Aclass AmbaFake(AmbaPioDevice): 3662307SN/A type = 'AmbaFake' 3672307SN/A cxx_header = "dev/arm/amba_fake.hh" 3682307SN/A ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3692307SN/A amba_id = 0; 3702680Sktlim@umich.edu 3712307SN/Aclass Pl011(Uart): 3722307SN/A type = 'Pl011' 3732307SN/A cxx_header = "dev/arm/pl011.hh" 3742307SN/A gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3752307SN/A int_num = Param.UInt32("Interrupt number that connects to GIC") 3762307SN/A end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3772307SN/A int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3782292SN/A 3792132SN/A def generateDeviceTree(self, state): 3802316SN/A node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 3813867Sbinkertn@umich.edu 0x1000, [int(self.int_num)]) 3823867Sbinkertn@umich.edu node.appendCompatible(["arm,pl011", "arm,primecell"]) 3833867Sbinkertn@umich.edu 3843867Sbinkertn@umich.edu # Hardcoded reference to the realview platform clocks, because the 3852316SN/A # clk_domain can only store one clock (i.e. it is not a VectorParam) 3863867Sbinkertn@umich.edu realview = self._parent.unproxy(self) 3872316SN/A node.append(FdtPropertyWords("clocks", 3882316SN/A [state.phandle(realview.mcc.osc_peripheral), 3892316SN/A state.phandle(realview.dcc.osc_smb)])) 3902316SN/A node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 3912316SN/A yield node 3922316SN/A 3932316SN/Aclass Sp804(AmbaPioDevice): 3942292SN/A type = 'Sp804' 3952292SN/A cxx_header = "dev/arm/timer_sp804.hh" 3962292SN/A gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3972292SN/A int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3982733Sktlim@umich.edu clock0 = Param.Clock('1MHz', "Clock speed of the input") 3992292SN/A int_num1 = Param.UInt32("Interrupt number that connects to GIC") 4002292SN/A clock1 = Param.Clock('1MHz', "Clock speed of the input") 4012733Sktlim@umich.edu amba_id = 0x00141804 4022292SN/A 4032292SN/Aclass A9GlobalTimer(BasicPioDevice): 4042292SN/A type = 'A9GlobalTimer' 4052292SN/A cxx_header = "dev/arm/timer_a9global.hh" 4062292SN/A gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 4072292SN/A int_num = Param.UInt32("Interrrupt number that connects to GIC") 4082292SN/A 4092292SN/Aclass CpuLocalTimer(BasicPioDevice): 4102292SN/A type = 'CpuLocalTimer' 4112292SN/A cxx_header = "dev/arm/timer_cpulocal.hh" 4122292SN/A gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 4133867Sbinkertn@umich.edu int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 4143867Sbinkertn@umich.edu int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 4152292SN/A 4163867Sbinkertn@umich.educlass GenericTimer(ClockedObject): 4172292SN/A type = 'GenericTimer' 4182292SN/A cxx_header = "dev/arm/generic_timer.hh" 4192292SN/A system = Param.ArmSystem(Parent.any, "system") 4202292SN/A gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 4212292SN/A int_phys_s = Param.UInt32("Physical (S) timer interrupt number") 4222292SN/A int_phys_ns = Param.UInt32("Physical (NS) timer interrupt number") 4232292SN/A int_virt = Param.UInt32("Virtual timer interrupt number") 4242702Sktlim@umich.edu int_hyp = Param.UInt32("Hypervisor timer interrupt number") 4252292SN/A 4262292SN/A def generateDeviceTree(self, state): 4272292SN/A node = FdtNode("timer") 4282292SN/A 4292292SN/A node.appendCompatible(["arm,cortex-a15-timer", 4302292SN/A "arm,armv7-timer", 4312292SN/A "arm,armv8-timer"]) 4322292SN/A node.append(FdtPropertyWords("interrupts", [ 4332292SN/A 1, int(self.int_phys_s) - 16, 0xf08, 4342292SN/A 1, int(self.int_phys_ns) - 16, 0xf08, 4352292SN/A 1, int(self.int_virt) - 16, 0xf08, 4362292SN/A 1, int(self.int_hyp) - 16, 0xf08, 4373867Sbinkertn@umich.edu ])) 4383867Sbinkertn@umich.edu clock = state.phandle(self.clk_domain.unproxy(self)) 4392292SN/A node.append(FdtPropertyWords("clocks", clock)) 4403867Sbinkertn@umich.edu 4412292SN/A yield node 4422292SN/A 4432292SN/Aclass GenericTimerMem(PioDevice): 4442292SN/A type = 'GenericTimerMem' 4452292SN/A cxx_header = "dev/arm/generic_timer.hh" 4462292SN/A gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 4472292SN/A 4482292SN/A base = Param.Addr(0, "Base address") 4492292SN/A 4502292SN/A int_phys = Param.UInt32("Interrupt number") 4512292SN/A int_virt = Param.UInt32("Interrupt number") 4522292SN/A 4532292SN/Aclass PL031(AmbaIntDevice): 4542292SN/A type = 'PL031' 4552292SN/A cxx_header = "dev/arm/rtc_pl031.hh" 4562292SN/A time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 4572292SN/A amba_id = 0x00341031 4582292SN/A 4592292SN/A def generateDeviceTree(self, state): 4602292SN/A node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 4612292SN/A 0x1000, [int(self.int_num)]) 4622292SN/A 4632292SN/A node.appendCompatible(["arm,pl031", "arm,primecell"]) 4642292SN/A clock = state.phandle(self.clk_domain.unproxy(self)) 4652292SN/A node.append(FdtPropertyWords("clocks", clock)) 4665606Snate@binkert.org 4674035Sktlim@umich.edu yield node 4682292SN/A 4692292SN/Aclass Pl050(AmbaIntDevice): 4702292SN/A type = 'Pl050' 4712292SN/A cxx_header = "dev/arm/kmi.hh" 4722680Sktlim@umich.edu amba_id = 0x00141050 4732292SN/A 4744035Sktlim@umich.edu ps2 = Param.PS2Device("PS/2 device") 4752680Sktlim@umich.edu 4762292SN/A def generateDeviceTree(self, state): 4772680Sktlim@umich.edu node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 4782292SN/A 0x1000, [int(self.int_num)]) 4792292SN/A 4802292SN/A node.appendCompatible(["arm,pl050", "arm,primecell"]) 4812292SN/A clock = state.phandle(self.clk_domain.unproxy(self)) 4822316SN/A node.append(FdtPropertyWords("clocks", clock)) 4832292SN/A 4842292SN/A yield node 4852292SN/A 4862292SN/Aclass Pl111(AmbaDmaDevice): 4872292SN/A type = 'Pl111' 4882292SN/A cxx_header = "dev/arm/pl111.hh" 4894035Sktlim@umich.edu pixel_clock = Param.Clock('24MHz', "Pixel clock") 4902292SN/A vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4912292SN/A amba_id = 0x00141111 4922292SN/A enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4932292SN/A 4942292SN/Aclass HDLcd(AmbaDmaDevice): 4952292SN/A type = 'HDLcd' 4962292SN/A cxx_header = "dev/arm/hdlcd.hh" 4972292SN/A vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4982292SN/A "display") 4992292SN/A amba_id = 0x00141000 5002292SN/A workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 5012292SN/A "selector order in some kernels") 5022292SN/A workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 5032292SN/A "DMA line count (off by 1)") 5042292SN/A enable_capture = Param.Bool(True, "capture frame to " 5052292SN/A "system.framebuffer.{extension}") 5062292SN/A frame_format = Param.ImageFormat("Auto", 5072292SN/A "image format of the captured frame") 5082292SN/A 5092292SN/A pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 5102292SN/A 5112292SN/A pxl_clk = Param.ClockDomain("Pixel clock source") 5122316SN/A pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 5133795Sgblack@eecs.umich.edu virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 5144636Sgblack@eecs.umich.edu "in KVM mode") 5152316SN/A 5162292SN/A def generateDeviceTree(self, state): 5172316SN/A # Interrupt number is hardcoded; it is not a property of this class 5182316SN/A node = self.generateBasicPioDeviceNode(state, 'hdlcd', 5192316SN/A self.pio_addr, 0x1000, [63]) 5202316SN/A 5212316SN/A node.appendCompatible(["arm,hdlcd"]) 5222316SN/A node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 5232316SN/A node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 5242316SN/A 5252316SN/A # This driver is disabled by default since the required DT nodes 5262316SN/A # haven't been standardized yet. To use it, override this status to 5274035Sktlim@umich.edu # "ok" and add the display configuration nodes required by the driver. 5282316SN/A # See the driver for more information. 5292316SN/A node.append(FdtPropertyStrings("status", ["disabled"])) 5302316SN/A 5312316SN/A yield node 5322316SN/A 5332316SN/Aclass RealView(Platform): 5342316SN/A type = 'RealView' 5352316SN/A cxx_header = "dev/arm/realview.hh" 5362316SN/A system = Param.System(Parent.any, "system") 5372680Sktlim@umich.edu _mem_regions = [(Addr(0), Addr('256MB'))] 5382316SN/A 5392316SN/A def _on_chip_devices(self): 5402292SN/A return [] 5412680Sktlim@umich.edu 5422292SN/A def _off_chip_devices(self): 5432292SN/A return [] 5442292SN/A 5452316SN/A _off_chip_ranges = [] 5462292SN/A 5472292SN/A def _attach_device(self, device, bus, dma_ports=None): 5482292SN/A if hasattr(device, "pio"): 5492680Sktlim@umich.edu device.pio = bus.master 5502292SN/A if hasattr(device, "dma"): 5512292SN/A if dma_ports is None: 5522292SN/A device.dma = bus.slave 5532292SN/A else: 5542292SN/A dma_ports.append(device.dma) 5552292SN/A 5562292SN/A def _attach_io(self, devices, *args, **kwargs): 5572292SN/A for d in devices: 5582292SN/A self._attach_device(d, *args, **kwargs) 5592843Sktlim@umich.edu 5602843Sktlim@umich.edu def _attach_clk(self, devices, clkdomain): 5612843Sktlim@umich.edu for d in devices: 5622316SN/A if hasattr(d, "clk_domain"): 5632316SN/A d.clk_domain = clkdomain 5642316SN/A 5653867Sbinkertn@umich.edu def attachPciDevices(self): 5662875Sksewell@umich.edu pass 5672875Sksewell@umich.edu 5683867Sbinkertn@umich.edu def enableMSIX(self): 5693867Sbinkertn@umich.edu pass 5702292SN/A 5712316SN/A def onChipIOClkDomain(self, clkdomain): 5722316SN/A self._attach_clk(self._on_chip_devices(), clkdomain) 5733867Sbinkertn@umich.edu 5742292SN/A def offChipIOClkDomain(self, clkdomain): 5752292SN/A self._attach_clk(self._off_chip_devices(), clkdomain) 5764035Sktlim@umich.edu 5774035Sktlim@umich.edu def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 5784035Sktlim@umich.edu self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 5794035Sktlim@umich.edu if bridge: 5802292SN/A bridge.ranges = self._off_chip_ranges 5812292SN/A 5822292SN/A def attachIO(self, *args, **kwargs): 5832292SN/A self._attach_io(self._off_chip_devices(), *args, **kwargs) 5842292SN/A 5852292SN/A def setupBootLoader(self, mem_bus, cur_sys, loc): 5862877Sksewell@umich.edu cur_sys.bootmem = SimpleMemory( 5872702Sktlim@umich.edu range = AddrRange('2GB', size = '64MB'), 5882702Sktlim@umich.edu conf_table_reported = False) 5892702Sktlim@umich.edu if mem_bus is not None: 5902292SN/A cur_sys.bootmem.port = mem_bus.master 5912292SN/A cur_sys.boot_loader = loc('boot.arm') 5922292SN/A cur_sys.atags_addr = 0x100 5932292SN/A cur_sys.load_offset = 0 5942292SN/A 5952292SN/A def generateDeviceTree(self, state): 5962292SN/A node = FdtNode("/") # Things in this module need to end up in the root 5972292SN/A node.append(FdtPropertyWords("interrupt-parent", 5983867Sbinkertn@umich.edu state.phandle(self.gic))) 5992292SN/A 6003867Sbinkertn@umich.edu for device in [getattr(self, c) for c in self._children]: 6012292SN/A if issubclass(type(device), SimObject): 6022292SN/A subnode = device.generateDeviceTree(state) 6032292SN/A node.append(subnode) 6042292SN/A 6052292SN/A yield node 6062292SN/A 6072292SN/A def annotateCpuDeviceNode(self, cpu, state): 6082292SN/A cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 6092292SN/A cpu.append(FdtPropertyWords("cpu-release-addr", \ 6102292SN/A state.addrCells(0x8000fff8))) 6112292SN/A 6122292SN/A# Reference for memory map and interrupt number 6132292SN/A# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 6142292SN/A# Chapter 4: Programmer's Reference 6152292SN/Aclass RealViewPBX(RealView): 6162292SN/A uart = Pl011(pio_addr=0x10009000, int_num=44) 6172292SN/A realview_io = RealViewCtrl(pio_addr=0x10000000) 6182292SN/A mcc = VExpressMCC() 6192292SN/A dcc = CoreTile2A15DCC() 6202292SN/A gic = Pl390() 6212292SN/A pci_host = GenericPciHost( 6222292SN/A conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 6232292SN/A pci_pio_base=0) 6242292SN/A timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 6252292SN/A timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 6262292SN/A global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 6272292SN/A local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 6282316SN/A pio_addr=0x1f000600) 6292292SN/A clcd = Pl111(pio_addr=0x10020000, int_num=55) 6302292SN/A kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard()) 6312292SN/A kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit()) 6322292SN/A a9scu = A9SCU(pio_addr=0x1f000000) 6332292SN/A cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 6342292SN/A io_shift = 1, ctrl_offset = 2, Command = 0x1, 6354035Sktlim@umich.edu BAR0 = 0x18000000, BAR0Size = '16B', 6362292SN/A BAR1 = 0x18000100, BAR1Size = '1B', 6372292SN/A BAR0LegacyIO = True, BAR1LegacyIO = True) 6384035Sktlim@umich.edu 6392292SN/A 6403640Sktlim@umich.edu l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 6412316SN/A flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 6422316SN/A fake_mem=True) 6432292SN/A dmac_fake = AmbaFake(pio_addr=0x10030000) 6443633Sktlim@umich.edu uart1_fake = AmbaFake(pio_addr=0x1000a000) 6453633Sktlim@umich.edu uart2_fake = AmbaFake(pio_addr=0x1000b000) 6463633Sktlim@umich.edu uart3_fake = AmbaFake(pio_addr=0x1000c000) 6473633Sktlim@umich.edu smc_fake = AmbaFake(pio_addr=0x100e1000) 6484035Sktlim@umich.edu sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6494035Sktlim@umich.edu watchdog_fake = AmbaFake(pio_addr=0x10010000) 6504035Sktlim@umich.edu gpio0_fake = AmbaFake(pio_addr=0x10013000) 6512292SN/A gpio1_fake = AmbaFake(pio_addr=0x10014000) 6522292SN/A gpio2_fake = AmbaFake(pio_addr=0x10015000) 6532292SN/A ssp_fake = AmbaFake(pio_addr=0x1000d000) 6543633Sktlim@umich.edu sci_fake = AmbaFake(pio_addr=0x1000e000) 6553640Sktlim@umich.edu aaci_fake = AmbaFake(pio_addr=0x10004000) 6562292SN/A mmc_fake = AmbaFake(pio_addr=0x10005000) 6573633Sktlim@umich.edu rtc = PL031(pio_addr=0x10017000, int_num=42) 6583633Sktlim@umich.edu energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 6592292SN/A 6602292SN/A 6612292SN/A # Attach I/O devices that are on chip and also set the appropriate 6622292SN/A # ranges for the bridge 6632292SN/A def attachOnChipIO(self, bus, bridge): 6643640Sktlim@umich.edu self.gic.pio = bus.master 6652292SN/A self.l2x0_fake.pio = bus.master 6662292SN/A self.a9scu.pio = bus.master 6672292SN/A self.global_timer.pio = bus.master 6684035Sktlim@umich.edu self.local_cpu_timer.pio = bus.master 6695704Snate@binkert.org # Bridge ranges based on excluding what is part of on-chip I/O 6704035Sktlim@umich.edu # (gic, l2x0, a9scu, local_cpu_timer) 6714035Sktlim@umich.edu bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6723640Sktlim@umich.edu self.a9scu.pio_addr - 1), 6733640Sktlim@umich.edu AddrRange(self.flash_fake.pio_addr, 6743640Sktlim@umich.edu self.flash_fake.pio_addr + \ 6753640Sktlim@umich.edu self.flash_fake.pio_size - 1)] 6763640Sktlim@umich.edu 6773640Sktlim@umich.edu # Set the clock domain for IO objects that are considered 6783640Sktlim@umich.edu # to be "close" to the cores. 6793640Sktlim@umich.edu def onChipIOClkDomain(self, clkdomain): 6803640Sktlim@umich.edu self.gic.clk_domain = clkdomain 6813640Sktlim@umich.edu self.l2x0_fake.clk_domain = clkdomain 6823640Sktlim@umich.edu self.a9scu.clkdomain = clkdomain 6833640Sktlim@umich.edu self.local_cpu_timer.clk_domain = clkdomain 6843640Sktlim@umich.edu 6853640Sktlim@umich.edu # Attach I/O devices to specified bus object. Can't do this 6861060SN/A # earlier, since the bus object itself is typically defined at the 6874035Sktlim@umich.edu # System level. 6884035Sktlim@umich.edu def attachIO(self, bus): 6893634Sktlim@umich.edu self.uart.pio = bus.master 6904035Sktlim@umich.edu self.realview_io.pio = bus.master 6914035Sktlim@umich.edu self.pci_host.pio = bus.master 6924035Sktlim@umich.edu self.timer0.pio = bus.master 6934035Sktlim@umich.edu self.timer1.pio = bus.master 6944035Sktlim@umich.edu self.clcd.pio = bus.master 6954035Sktlim@umich.edu self.clcd.dma = bus.slave 6964035Sktlim@umich.edu self.kmi0.pio = bus.master 6974035Sktlim@umich.edu self.kmi1.pio = bus.master 6984035Sktlim@umich.edu self.cf_ctrl.pio = bus.master 6995704Snate@binkert.org self.cf_ctrl.dma = bus.slave 7004035Sktlim@umich.edu self.dmac_fake.pio = bus.master 7014035Sktlim@umich.edu self.uart1_fake.pio = bus.master 7021060SN/A self.uart2_fake.pio = bus.master 7031060SN/A self.uart3_fake.pio = bus.master 7041060SN/A self.smc_fake.pio = bus.master 7052316SN/A self.sp810_fake.pio = bus.master 7061060SN/A self.watchdog_fake.pio = bus.master 7073867Sbinkertn@umich.edu self.gpio0_fake.pio = bus.master 7083867Sbinkertn@umich.edu self.gpio1_fake.pio = bus.master 7091060SN/A self.gpio2_fake.pio = bus.master 7103867Sbinkertn@umich.edu self.ssp_fake.pio = bus.master 7112292SN/A self.sci_fake.pio = bus.master 7121060SN/A self.aaci_fake.pio = bus.master 7132292SN/A self.mmc_fake.pio = bus.master 7142292SN/A self.rtc.pio = bus.master 7152292SN/A self.flash_fake.pio = bus.master 7162680Sktlim@umich.edu self.energy_ctrl.pio = bus.master 7172292SN/A 7182680Sktlim@umich.edu # Set the clock domain for IO objects that are considered 7194035Sktlim@umich.edu # to be "far" away from the cores. 7202680Sktlim@umich.edu def offChipIOClkDomain(self, clkdomain): 7212292SN/A self.uart.clk_domain = clkdomain 7221061SN/A self.realview_io.clk_domain = clkdomain 7232292SN/A self.timer0.clk_domain = clkdomain 7242292SN/A self.timer1.clk_domain = clkdomain 7252292SN/A self.clcd.clk_domain = clkdomain 7262292SN/A self.kmi0.clk_domain = clkdomain 7272292SN/A self.kmi1.clk_domain = clkdomain 7282292SN/A self.cf_ctrl.clk_domain = clkdomain 7291061SN/A self.dmac_fake.clk_domain = clkdomain 7302292SN/A self.uart1_fake.clk_domain = clkdomain 7312292SN/A self.uart2_fake.clk_domain = clkdomain 7322292SN/A self.uart3_fake.clk_domain = clkdomain 7332292SN/A self.smc_fake.clk_domain = clkdomain 7341061SN/A self.sp810_fake.clk_domain = clkdomain 7352292SN/A self.watchdog_fake.clk_domain = clkdomain 7362292SN/A self.gpio0_fake.clk_domain = clkdomain 7372292SN/A self.gpio1_fake.clk_domain = clkdomain 7381061SN/A self.gpio2_fake.clk_domain = clkdomain 7392292SN/A self.ssp_fake.clk_domain = clkdomain 7401061SN/A self.sci_fake.clk_domain = clkdomain 7412292SN/A self.aaci_fake.clk_domain = clkdomain 7422292SN/A self.mmc_fake.clk_domain = clkdomain 7432292SN/A self.rtc.clk_domain = clkdomain 7441062SN/A self.flash_fake.clk_domain = clkdomain 7452935Sksewell@umich.edu self.energy_ctrl.clk_domain = clkdomain 7462292SN/A 7472935Sksewell@umich.edu# Reference for memory map and interrupt number 7484035Sktlim@umich.edu# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 7492292SN/A# Chapter 4: Programmer's Reference 7502292SN/Aclass RealViewEB(RealView): 7512292SN/A uart = Pl011(pio_addr=0x10009000, int_num=44) 7522292SN/A realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 7533093Sksewell@umich.edu mcc = VExpressMCC() 7542292SN/A dcc = CoreTile2A15DCC() 7552292SN/A gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 7562292SN/A timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 7572292SN/A timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 7582292SN/A clcd = Pl111(pio_addr=0x10020000, int_num=23) 7592292SN/A kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard()) 7602292SN/A kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit()) 7612292SN/A 7622292SN/A l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 7632292SN/A flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 7642292SN/A fake_mem=True) 7652292SN/A dmac_fake = AmbaFake(pio_addr=0x10030000) 7662292SN/A uart1_fake = AmbaFake(pio_addr=0x1000a000) 7672292SN/A uart2_fake = AmbaFake(pio_addr=0x1000b000) 7682292SN/A uart3_fake = AmbaFake(pio_addr=0x1000c000) 7692292SN/A smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 7702292SN/A smc_fake = AmbaFake(pio_addr=0x100e1000) 7713795Sgblack@eecs.umich.edu sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 7724636Sgblack@eecs.umich.edu watchdog_fake = AmbaFake(pio_addr=0x10010000) 7732292SN/A gpio0_fake = AmbaFake(pio_addr=0x10013000) 7742316SN/A gpio1_fake = AmbaFake(pio_addr=0x10014000) 7752292SN/A gpio2_fake = AmbaFake(pio_addr=0x10015000) 7762292SN/A ssp_fake = AmbaFake(pio_addr=0x1000d000) 7772292SN/A sci_fake = AmbaFake(pio_addr=0x1000e000) 7782292SN/A aaci_fake = AmbaFake(pio_addr=0x10004000) 7791062SN/A mmc_fake = AmbaFake(pio_addr=0x10005000) 7802292SN/A rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 7811060SN/A energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 7821060SN/A 7832292SN/A # Attach I/O devices that are on chip and also set the appropriate 7842292SN/A # ranges for the bridge 7852292SN/A def attachOnChipIO(self, bus, bridge): 7861061SN/A self.gic.pio = bus.master 7871060SN/A self.l2x0_fake.pio = bus.master 7881060SN/A # Bridge ranges based on excluding what is part of on-chip I/O 7891061SN/A # (gic, l2x0) 7901060SN/A bridge.ranges = [AddrRange(self.realview_io.pio_addr, 7911060SN/A self.gic.cpu_addr - 1), 7921060SN/A AddrRange(self.flash_fake.pio_addr, Addr.max)] 7932292SN/A 7943867Sbinkertn@umich.edu # Set the clock domain for IO objects that are considered 7952292SN/A # to be "close" to the cores. 7963867Sbinkertn@umich.edu def onChipIOClkDomain(self, clkdomain): 7972292SN/A self.gic.clk_domain = clkdomain 7982292SN/A self.l2x0_fake.clk_domain = clkdomain 7992292SN/A 8002292SN/A # Attach I/O devices to specified bus object. Can't do this 8012292SN/A # earlier, since the bus object itself is typically defined at the 8022292SN/A # System level. 8032292SN/A def attachIO(self, bus): 8042292SN/A self.uart.pio = bus.master 8054035Sktlim@umich.edu self.realview_io.pio = bus.master 8064035Sktlim@umich.edu self.pci_host.pio = bus.master 8072292SN/A self.timer0.pio = bus.master 8084035Sktlim@umich.edu self.timer1.pio = bus.master 8094035Sktlim@umich.edu self.clcd.pio = bus.master 8104035Sktlim@umich.edu self.clcd.dma = bus.slave 8114035Sktlim@umich.edu self.kmi0.pio = bus.master 8124035Sktlim@umich.edu self.kmi1.pio = bus.master 8134035Sktlim@umich.edu self.dmac_fake.pio = bus.master 8144035Sktlim@umich.edu self.uart1_fake.pio = bus.master 8154035Sktlim@umich.edu self.uart2_fake.pio = bus.master 8164035Sktlim@umich.edu self.uart3_fake.pio = bus.master 8174035Sktlim@umich.edu self.smc_fake.pio = bus.master 8185557Sktlim@umich.edu self.sp810_fake.pio = bus.master 8194035Sktlim@umich.edu self.watchdog_fake.pio = bus.master 8204035Sktlim@umich.edu self.gpio0_fake.pio = bus.master 8214035Sktlim@umich.edu self.gpio1_fake.pio = bus.master 8224035Sktlim@umich.edu self.gpio2_fake.pio = bus.master 8234035Sktlim@umich.edu self.ssp_fake.pio = bus.master 8244035Sktlim@umich.edu self.sci_fake.pio = bus.master 8254035Sktlim@umich.edu self.aaci_fake.pio = bus.master 8261060SN/A self.mmc_fake.pio = bus.master 8271060SN/A self.rtc_fake.pio = bus.master 8281060SN/A self.flash_fake.pio = bus.master 8291061SN/A self.smcreg_fake.pio = bus.master 8301060SN/A self.energy_ctrl.pio = bus.master 8312292SN/A 8321060SN/A # Set the clock domain for IO objects that are considered 8331060SN/A # to be "far" away from the cores. 8341060SN/A def offChipIOClkDomain(self, clkdomain): 8352316SN/A self.uart.clk_domain = clkdomain 8362316SN/A self.realview_io.clk_domain = clkdomain 8372316SN/A self.timer0.clk_domain = clkdomain 8382316SN/A self.timer1.clk_domain = clkdomain 8392316SN/A self.clcd.clk_domain = clkdomain 8401060SN/A self.kmi0.clk_domain = clkdomain 8411060SN/A self.kmi1.clk_domain = clkdomain 8422292SN/A self.dmac_fake.clk_domain = clkdomain 8431060SN/A self.uart1_fake.clk_domain = clkdomain 8441060SN/A self.uart2_fake.clk_domain = clkdomain 8451060SN/A self.uart3_fake.clk_domain = clkdomain 8462292SN/A self.smc_fake.clk_domain = clkdomain 8472316SN/A self.sp810_fake.clk_domain = clkdomain 8481060SN/A self.watchdog_fake.clk_domain = clkdomain 8491060SN/A self.gpio0_fake.clk_domain = clkdomain 8502292SN/A self.gpio1_fake.clk_domain = clkdomain 8512292SN/A self.gpio2_fake.clk_domain = clkdomain 8521060SN/A self.ssp_fake.clk_domain = clkdomain 8532292SN/A self.sci_fake.clk_domain = clkdomain 8542292SN/A self.aaci_fake.clk_domain = clkdomain 8552292SN/A self.mmc_fake.clk_domain = clkdomain 8562292SN/A self.rtc.clk_domain = clkdomain 8572292SN/A self.flash_fake.clk_domain = clkdomain 8582292SN/A self.smcreg_fake.clk_domain = clkdomain 8592292SN/A self.energy_ctrl.clk_domain = clkdomain 8602292SN/A 8612292SN/Aclass VExpress_EMM(RealView): 8622292SN/A _mem_regions = [(Addr('2GB'), Addr('2GB'))] 8632292SN/A 8642132SN/A # Ranges based on excluding what is part of on-chip I/O (gic, 8652316SN/A # a9scu) 8662316SN/A _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 8671060SN/A AddrRange(0x30000000, size='256MB'), 8681060SN/A AddrRange(0x40000000, size='512MB'), 8692292SN/A AddrRange(0x18000000, size='64MB'), 8701060SN/A AddrRange(0x1C000000, size='64MB')] 8711060SN/A 8722292SN/A # Platform control device (off-chip) 8731060SN/A realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 8741062SN/A idreg=0x02250000, pio_addr=0x1C010000) 8751062SN/A 8762292SN/A mcc = VExpressMCC() 8772292SN/A dcc = CoreTile2A15DCC() 8781060SN/A 8792292SN/A ### On-chip devices ### 8802292SN/A gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 8812935Sksewell@umich.edu vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 8824636Sgblack@eecs.umich.edu 8832292SN/A local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 8841060SN/A pio_addr=0x2C080000) 8851060SN/A 8861060SN/A hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 8871061SN/A pio_addr=0x2b000000, int_num=117, 8881061SN/A workaround_swap_rb=True) 8892292SN/A 8901060SN/A def _on_chip_devices(self): 8911060SN/A devices = [ 8921060SN/A self.gic, self.vgic, 8931060SN/A self.local_cpu_timer 8941062SN/A ] 8951060SN/A if hasattr(self, "gicv2m"): 8961060SN/A devices.append(self.gicv2m) 8972292SN/A devices.append(self.hdlcd) 8982292SN/A return devices 8992292SN/A 9002292SN/A ### Off-chip devices ### 9011060SN/A uart = Pl011(pio_addr=0x1c090000, int_num=37) 9021062SN/A pci_host = GenericPciHost( 9031062SN/A conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 9042292SN/A pci_pio_base=0) 9052292SN/A 9062292SN/A generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30, 9072292SN/A int_virt=27, int_hyp=26) 9081062SN/A timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 9092292SN/A timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 9102292SN/A clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 9112935Sksewell@umich.edu kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 9122935Sksewell@umich.edu kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 9134636Sgblack@eecs.umich.edu cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 9144636Sgblack@eecs.umich.edu io_shift = 2, ctrl_offset = 2, Command = 0x1, 9152935Sksewell@umich.edu BAR0 = 0x1C1A0000, BAR0Size = '256B', 9162292SN/A BAR1 = 0x1C1A0100, BAR1Size = '4096B', 9172292SN/A BAR0LegacyIO = True, BAR1LegacyIO = True) 9185108Sgblack@eecs.umich.edu 9195108Sgblack@eecs.umich.edu vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 9205108Sgblack@eecs.umich.edu conf_table_reported = False) 9212292SN/A rtc = PL031(pio_addr=0x1C170000, int_num=36) 9222292SN/A 9235108Sgblack@eecs.umich.edu l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 9242292SN/A uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 9252292SN/A uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 9262292SN/A uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 9275108Sgblack@eecs.umich.edu sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 9285108Sgblack@eecs.umich.edu watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 9292292SN/A aaci_fake = AmbaFake(pio_addr=0x1C040000) 9302292SN/A lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 9311060SN/A usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 9322292SN/A mmc_fake = AmbaFake(pio_addr=0x1c050000) 9332292SN/A energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 9342292SN/A 9351060SN/A def _off_chip_devices(self): 9361060SN/A devices = [ 9371060SN/A self.uart, 9381060SN/A self.realview_io, 9391062SN/A self.pci_host, 9401063SN/A self.timer0, 9412292SN/A self.timer1, 9422307SN/A self.clcd, 9432307SN/A self.kmi0, 9442349SN/A self.kmi1, 9452307SN/A self.cf_ctrl, 9461060SN/A self.rtc, 9471060SN/A self.vram, 9481061SN/A self.l2x0_fake, 9491060SN/A self.uart1_fake, 9502292SN/A self.uart2_fake, 9511060SN/A self.uart3_fake, 9521060SN/A self.sp810_fake, 9531060SN/A self.watchdog_fake, 9542292SN/A self.aaci_fake, 9552292SN/A self.lan_fake, 9562316SN/A self.usb_fake, 9572316SN/A self.mmc_fake, 9581061SN/A self.energy_ctrl, 9591061SN/A ] 9601061SN/A # Try to attach the I/O if it exists 9612292SN/A if hasattr(self, "ide"): 9621062SN/A devices.append(self.ide) 9632292SN/A if hasattr(self, "ethernet"): 9642348SN/A devices.append(self.ethernet) 9652292SN/A return devices 9662292SN/A 9672316SN/A # Attach any PCI devices that are supported 9682316SN/A def attachPciDevices(self): 9692316SN/A self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 9702316SN/A InterruptLine=1, InterruptPin=1) 9712316SN/A self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 9725557Sktlim@umich.edu InterruptLine=2, InterruptPin=2) 9732292SN/A 9742292SN/A def enableMSIX(self): 9752292SN/A self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 9762292SN/A self.gicv2m = Gicv2m() 9772292SN/A self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 9781061SN/A 9791061SN/A def setupBootLoader(self, mem_bus, cur_sys, loc): 9801061SN/A cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 9811061SN/A conf_table_reported = False) 9821061SN/A if mem_bus is not None: 9831062SN/A cur_sys.bootmem.port = mem_bus.master 9841062SN/A if not cur_sys.boot_loader: 9851061SN/A cur_sys.boot_loader = loc('boot_emm.arm') 9862292SN/A cur_sys.atags_addr = 0x8000000 9875557Sktlim@umich.edu cur_sys.load_offset = 0x80000000 9884035Sktlim@umich.edu 9894035Sktlim@umich.educlass VExpress_EMM64(VExpress_EMM): 9904035Sktlim@umich.edu # Three memory regions are specified totalling 512GB 9914035Sktlim@umich.edu _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 9924035Sktlim@umich.edu (Addr('512GB'), Addr('480GB'))] 9932292SN/A pci_host = GenericPciHost( 9942292SN/A conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 9952292SN/A pci_pio_base=0x2f000000) 9962292SN/A 9972316SN/A def setupBootLoader(self, mem_bus, cur_sys, loc): 9982292SN/A cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 9992292SN/A conf_table_reported=False) 10002292SN/A if mem_bus is not None: 10012292SN/A cur_sys.bootmem.port = mem_bus.master 10022292SN/A if not cur_sys.boot_loader: 10032292SN/A cur_sys.boot_loader = loc('boot_emm.arm64') 10042292SN/A cur_sys.atags_addr = 0x8000000 10051061SN/A cur_sys.load_offset = 0x80000000 10062292SN/A 10071061SN/Aclass VExpress_GEM5_V1(RealView): 10081061SN/A """ 10091060SN/AThe VExpress gem5 memory map is loosely based on a modified 10101060SN/AVersatile Express RS1 memory map. 10112316SN/A 10122292SN/AThe gem5 platform has been designed to implement a subset of the 10132316SN/Aoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 10142132SN/Awhen possible, adhere to the Versatile Express memory map. Non-PCI 10152132SN/Aoff-chip devices that are gem5-specific should live in the CS5 memory 10164035Sktlim@umich.eduspace to avoid conflicts with existing devices that we might want to 10174035Sktlim@umich.edumodel in the future. Such devices should normally have interrupts in 10184035Sktlim@umich.eduthe gem5-specific SPI range. 10192316SN/A 10204035Sktlim@umich.eduOn-chip peripherals are loosely modeled after the ARM CoreTile Express 10212310SN/AA15x2 A7x3 memory and interrupt map. In particular, the GIC and 10222310SN/AGeneric Timer have the same interrupt lines and base addresses. Other 10232310SN/Aon-chip devices are gem5 specific. 10242733Sktlim@umich.edu 10252316SN/AUnlike the original Versatile Express RS2 extended platform, gem5 implements a 10262316SN/Alarge contigious DRAM space, without aliases or holes, starting at the 10272316SN/A2GiB boundary. This means that PCI memory is limited to 1GiB. 10282732Sktlim@umich.edu 10291060SN/AMemory map: 10302733Sktlim@umich.edu 0x00000000-0x03ffffff: Boot memory (CS0) 10311060SN/A 0x04000000-0x07ffffff: Reserved 10322918Sktlim@umich.edu 0x08000000-0x0bffffff: Reserved (CS0 alias) 10332918Sktlim@umich.edu 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 10342918Sktlim@umich.edu 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 10352918Sktlim@umich.edu 0x10000000-0x1000ffff: gem5 energy controller 10362918Sktlim@umich.edu 0x10010000-0x1001ffff: gem5 pseudo-ops 10372918Sktlim@umich.edu 10382112SN/A 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 10392316SN/A 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 10402316SN/A 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 10412292SN/A 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 10425557Sktlim@umich.edu 0x1c060000-0x1c06ffff: KMI0 (keyboard) 10432316SN/A 0x1c070000-0x1c07ffff: KMI1 (mouse) 10442316SN/A 0x1c090000-0x1c09ffff: UART0 10452316SN/A 0x1c0a0000-0x1c0affff: UART1 (reserved) 10462310SN/A 0x1c0b0000-0x1c0bffff: UART2 (reserved) 10474035Sktlim@umich.edu 0x1c0c0000-0x1c0cffff: UART3 (reserved) 10484035Sktlim@umich.edu 0x1c170000-0x1c17ffff: RTC 10492733Sktlim@umich.edu 10502316SN/A 0x20000000-0x3fffffff: On-chip peripherals: 10512732Sktlim@umich.edu 0x2b000000-0x2b00ffff: HDLCD 10522316SN/A 10532733Sktlim@umich.edu 0x2c001000-0x2c001fff: GIC (distributor) 10542292SN/A 0x2c002000-0x2c0020ff: GIC (CPU interface) 10552316SN/A 0x2c004000-0x2c005fff: vGIC (HV) 10562292SN/A 0x2c006000-0x2c007fff: vGIC (VCPU) 10572316SN/A 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 10582316SN/A 10592316SN/A 0x2d000000-0x2d00ffff: GPU (reserved) 10602292SN/A 10612316SN/A 0x2f000000-0x2fffffff: PCI IO space 10622316SN/A 0x30000000-0x3fffffff: PCI config space 10632316SN/A 10642316SN/A 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 10652316SN/A 10662316SN/A 0x80000000-X: DRAM 10672316SN/A 10682292SN/AInterrupts: 10692316SN/A 0- 15: Software generated interrupts (SGIs) 10702316SN/A 16- 31: On-chip private peripherals (PPIs) 10712292SN/A 25 : vgic 10722316SN/A 26 : generic_timer (hyp) 10732292SN/A 27 : generic_timer (virt) 10744035Sktlim@umich.edu 28 : Reserved (Legacy FIQ) 10754035Sktlim@umich.edu 29 : generic_timer (phys, sec) 10764035Sktlim@umich.edu 30 : generic_timer (phys, non-sec) 10774288Sktlim@umich.edu 31 : Reserved (Legacy IRQ) 10784288Sktlim@umich.edu 32- 95: Mother board peripherals (SPIs) 10794035Sktlim@umich.edu 32 : Reserved (SP805) 10804035Sktlim@umich.edu 33 : Reserved (IOFPGA SW int) 10814035Sktlim@umich.edu 34-35: Reserved (SP804) 10822316SN/A 36 : RTC 10832316SN/A 37-40: uart0-uart3 10842353SN/A 41-42: Reserved (PL180) 10852316SN/A 43 : Reserved (AACI) 10861060SN/A 44-45: kmi0-kmi1 10871060SN/A 46 : Reserved (CLCD) 10882301SN/A 47 : Reserved (Ethernet) 10892132SN/A 48 : Reserved (USB) 10902362SN/A 95-255: On-chip interrupt sources (we use these for 10912362SN/A gem5-specific devices, SPIs) 10923577Sgblack@eecs.umich.edu 95 : HDLCD 10932362SN/A 96- 98: GPU (reserved) 10942362SN/A 100-103: PCI 10953126Sktlim@umich.edu 256-319: MSI frame 0 (gem5-specific, SPIs) 10962362SN/A 320-511: Unused 10972362SN/A 10982362SN/A """ 10992362SN/A 11002362SN/A # Everything above 2GiB is memory 11015953Ssaidi@eecs.umich.edu _mem_regions = [(Addr('2GB'), Addr('510GB'))] 11025953Ssaidi@eecs.umich.edu 11035953Ssaidi@eecs.umich.edu _off_chip_ranges = [ 11045953Ssaidi@eecs.umich.edu # CS1-CS5 11055953Ssaidi@eecs.umich.edu AddrRange(0x0c000000, 0x1fffffff), 11065953Ssaidi@eecs.umich.edu # External AXI interface (PCI) 11072362SN/A AddrRange(0x2f000000, 0x7fffffff), 11082362SN/A ] 11092132SN/A 11102292SN/A # Platform control device (off-chip) 11112292SN/A realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 11124046Sbinkertn@umich.edu idreg=0x02250000, pio_addr=0x1c010000) 11134046Sbinkertn@umich.edu mcc = VExpressMCC() 11142292SN/A dcc = CoreTile2A15DCC() 11151060SN/A 11161060SN/A ### On-chip devices ### 11172292SN/A gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 11182292SN/A it_lines=512) 11193771Sgblack@eecs.umich.edu vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 11202292SN/A gicv2m = Gicv2m() 11211060SN/A gicv2m.frames = [ 11221062SN/A Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 11232353SN/A ] 11242353SN/A 11252353SN/A generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30, 11262292SN/A int_virt=27, int_hyp=26) 11272292SN/A 11281060SN/A hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 11294035Sktlim@umich.edu pio_addr=0x2b000000, int_num=95) 11304035Sktlim@umich.edu 11314035Sktlim@umich.edu def _on_chip_devices(self): 11324035Sktlim@umich.edu return [ 11331060SN/A self.gic, self.vgic, self.gicv2m, 11341060SN/A self.hdlcd, 11351060SN/A self.generic_timer, 11361060SN/A ] 11371061SN/A 11381060SN/A ### Off-chip devices ### 11392292SN/A clock24MHz = SrcClockDomain(clock="24MHz", 11401060SN/A voltage_domain=VoltageDomain(voltage="3.3V")) 11412935Sksewell@umich.edu 11422935Sksewell@umich.edu uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 11433093Sksewell@umich.edu 11443093Sksewell@umich.edu kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 11452965Sksewell@umich.edu kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 11462965Sksewell@umich.edu 11472965Sksewell@umich.edu rtc = PL031(pio_addr=0x1c170000, int_num=36) 11482965Sksewell@umich.edu 11493093Sksewell@umich.edu ### gem5-specific off-chip devices ### 11502292SN/A pci_host = GenericArmPciHost( 11512292SN/A conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 11522292SN/A pci_pio_base=0x2f000000, 11534035Sktlim@umich.edu int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 11544035Sktlim@umich.edu 11552292SN/A energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 11562292SN/A 11572292SN/A 11582292SN/A def _off_chip_devices(self): 11592292SN/A return [ 11602292SN/A self.realview_io, 11612292SN/A self.uart0, 11622292SN/A self.kmi0, 11632292SN/A self.kmi1, 11642292SN/A self.rtc, 11651061SN/A self.pci_host, 11662292SN/A self.energy_ctrl, 11671061SN/A self.clock24MHz, 11682292SN/A ] 11691061SN/A 11701060SN/A def attachPciDevice(self, device, *args, **kwargs): 11712965Sksewell@umich.edu device.host = self.pci_host 11722965Sksewell@umich.edu self._attach_device(device, *args, **kwargs) 11732965Sksewell@umich.edu 11742965Sksewell@umich.edu def setupBootLoader(self, mem_bus, cur_sys, loc): 11752965Sksewell@umich.edu cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 11762965Sksewell@umich.edu conf_table_reported=False) 11772965Sksewell@umich.edu if mem_bus is not None: 11782965Sksewell@umich.edu cur_sys.bootmem.port = mem_bus.master 11792965Sksewell@umich.edu if not cur_sys.boot_loader: 11802965Sksewell@umich.edu cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 11812965Sksewell@umich.edu cur_sys.atags_addr = 0x8000000 11822965Sksewell@umich.edu cur_sys.load_offset = 0x80000000 11832965Sksewell@umich.edu 11842965Sksewell@umich.edu # Setup m5ops. It's technically not a part of the boot 11853221Sktlim@umich.edu # loader, but this is the only place we can configure the 11863221Sktlim@umich.edu # system. 11872965Sksewell@umich.edu cur_sys.m5ops_base = 0x10010000 11882965Sksewell@umich.edu 11892965Sksewell@umich.edu def generateDeviceTree(self, state): 11902965Sksewell@umich.edu # Generate using standard RealView function 11913221Sktlim@umich.edu dt = list(super(VExpress_GEM5_V1, self).generateDeviceTree(state)) 11922965Sksewell@umich.edu if len(dt) > 1: 11932965Sksewell@umich.edu raise Exception("System returned too many DT nodes") 11941060SN/A node = dt[0] 11951060SN/A 11961061SN/A node.appendCompatible(["arm,vexpress"]) 11971060SN/A node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 11982292SN/A node.append(FdtPropertyWords("arm,hbi", [0x0])) 11991060SN/A node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 12001060SN/A 12011060SN/A yield node 12021060SN/A