RealView.py revision 12116
1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 48from PciHost import * 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl 57from ClockDomain import SrcClockDomain 58from SubSystem import SubSystem 59 60# Platforms with KVM support should generally use in-kernel GIC 61# emulation. Use a GIC model that automatically switches between 62# gem5's GIC model and KVM's GIC model if KVM is available. 63try: 64 from KvmGic import MuxingKvmGic 65 kvm_gicv2_class = MuxingKvmGic 66except ImportError: 67 # KVM support wasn't compiled into gem5. Fallback to a 68 # software-only GIC. 69 kvm_gicv2_class = Pl390 70 pass 71 72class AmbaPioDevice(BasicPioDevice): 73 type = 'AmbaPioDevice' 74 abstract = True 75 cxx_header = "dev/arm/amba_device.hh" 76 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 77 78class AmbaIntDevice(AmbaPioDevice): 79 type = 'AmbaIntDevice' 80 abstract = True 81 cxx_header = "dev/arm/amba_device.hh" 82 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 83 int_num = Param.UInt32("Interrupt number that connects to GIC") 84 int_delay = Param.Latency("100ns", 85 "Time between action and interrupt generation by device") 86 87class AmbaDmaDevice(DmaDevice): 88 type = 'AmbaDmaDevice' 89 abstract = True 90 cxx_header = "dev/arm/amba_device.hh" 91 pio_addr = Param.Addr("Address for AMBA slave interface") 92 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 93 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 94 int_num = Param.UInt32("Interrupt number that connects to GIC") 95 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 96 97class A9SCU(BasicPioDevice): 98 type = 'A9SCU' 99 cxx_header = "dev/arm/a9scu.hh" 100 101class ArmPciIntRouting(Enum): vals = [ 102 'ARM_PCI_INT_STATIC', 103 'ARM_PCI_INT_DEV', 104 'ARM_PCI_INT_PIN', 105 ] 106 107class GenericArmPciHost(GenericPciHost): 108 type = 'GenericArmPciHost' 109 cxx_header = "dev/arm/pci_host.hh" 110 111 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 112 int_base = Param.Unsigned("PCI interrupt base") 113 int_count = Param.Unsigned("Maximum number of interrupts used by this host") 114 115class RealViewCtrl(BasicPioDevice): 116 type = 'RealViewCtrl' 117 cxx_header = "dev/arm/rv_ctrl.hh" 118 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 119 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 120 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 121 122class RealViewOsc(ClockDomain): 123 type = 'RealViewOsc' 124 cxx_header = "dev/arm/rv_ctrl.hh" 125 126 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 127 128 # TODO: We currently don't have the notion of a clock source, 129 # which means we have to associate oscillators with a voltage 130 # source. 131 voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 132 "Voltage domain") 133 134 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 135 # the individual core/logic tile reference manuals for details 136 # about the site/position/dcc/device allocation. 137 site = Param.UInt8("Board Site") 138 position = Param.UInt8("Position in device stack") 139 dcc = Param.UInt8("Daughterboard Configuration Controller") 140 device = Param.UInt8("Device ID") 141 142 freq = Param.Clock("Default frequency") 143 144class RealViewTemperatureSensor(SimObject): 145 type = 'RealViewTemperatureSensor' 146 cxx_header = "dev/arm/rv_ctrl.hh" 147 148 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 149 150 system = Param.System(Parent.any, "system") 151 152 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 153 # the individual core/logic tile reference manuals for details 154 # about the site/position/dcc/device allocation. 155 site = Param.UInt8("Board Site") 156 position = Param.UInt8("Position in device stack") 157 dcc = Param.UInt8("Daughterboard Configuration Controller") 158 device = Param.UInt8("Device ID") 159 160class VExpressMCC(SubSystem): 161 """ARM V2M-P1 Motherboard Configuration Controller 162 163This subsystem describes a subset of the devices that sit behind the 164motherboard configuration controller on the the ARM Motherboard 165Express (V2M-P1) motherboard. See ARM DUI 0447J for details. 166 """ 167 168 class Osc(RealViewOsc): 169 site, position, dcc = (0, 0, 0) 170 171 class Temperature(RealViewTemperatureSensor): 172 site, position, dcc = (0, 0, 0) 173 174 osc_mcc = Osc(device=0, freq="50MHz") 175 osc_clcd = Osc(device=1, freq="23.75MHz") 176 osc_peripheral = Osc(device=2, freq="24MHz") 177 osc_system_bus = Osc(device=4, freq="24MHz") 178 179 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 180 temp_crtl = Temperature(device=0) 181 182class CoreTile2A15DCC(SubSystem): 183 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 184 185This subsystem describes a subset of the devices that sit behind the 186daughterboard configuration controller on a CoreTile Express A15x2. See 187ARM DUI 0604E for details. 188 """ 189 190 class Osc(RealViewOsc): 191 site, position, dcc = (1, 0, 0) 192 193 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 194 osc_cpu = Osc(device=0, freq="60MHz") 195 osc_hsbm = Osc(device=4, freq="40MHz") 196 osc_pxl = Osc(device=5, freq="23.75MHz") 197 osc_smb = Osc(device=6, freq="50MHz") 198 osc_sys = Osc(device=7, freq="60MHz") 199 osc_ddr = Osc(device=8, freq="40MHz") 200 201class VGic(PioDevice): 202 type = 'VGic' 203 cxx_header = "dev/arm/vgic.hh" 204 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 205 platform = Param.Platform(Parent.any, "Platform this device is part of.") 206 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 207 hv_addr = Param.Addr(0, "Address for hv control") 208 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 209 # The number of list registers is not currently configurable at runtime. 210 ppint = Param.UInt32("HV maintenance interrupt number") 211 212class AmbaFake(AmbaPioDevice): 213 type = 'AmbaFake' 214 cxx_header = "dev/arm/amba_fake.hh" 215 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 216 amba_id = 0; 217 218class Pl011(Uart): 219 type = 'Pl011' 220 cxx_header = "dev/arm/pl011.hh" 221 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 222 int_num = Param.UInt32("Interrupt number that connects to GIC") 223 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 224 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 225 226class Sp804(AmbaPioDevice): 227 type = 'Sp804' 228 cxx_header = "dev/arm/timer_sp804.hh" 229 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 230 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 231 clock0 = Param.Clock('1MHz', "Clock speed of the input") 232 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 233 clock1 = Param.Clock('1MHz', "Clock speed of the input") 234 amba_id = 0x00141804 235 236class A9GlobalTimer(BasicPioDevice): 237 type = 'A9GlobalTimer' 238 cxx_header = "dev/arm/timer_a9global.hh" 239 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 240 int_num = Param.UInt32("Interrrupt number that connects to GIC") 241 242class CpuLocalTimer(BasicPioDevice): 243 type = 'CpuLocalTimer' 244 cxx_header = "dev/arm/timer_cpulocal.hh" 245 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 246 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 247 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 248 249class GenericTimer(SimObject): 250 type = 'GenericTimer' 251 cxx_header = "dev/arm/generic_timer.hh" 252 system = Param.ArmSystem(Parent.any, "system") 253 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 254 # @todo: for now only two timers per CPU is supported, which is the 255 # normal behaviour when security extensions are disabled. 256 int_phys = Param.UInt32("Physical timer interrupt number") 257 int_virt = Param.UInt32("Virtual timer interrupt number") 258 259class GenericTimerMem(PioDevice): 260 type = 'GenericTimerMem' 261 cxx_header = "dev/arm/generic_timer.hh" 262 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 263 264 base = Param.Addr(0, "Base address") 265 266 int_phys = Param.UInt32("Interrupt number") 267 int_virt = Param.UInt32("Interrupt number") 268 269class PL031(AmbaIntDevice): 270 type = 'PL031' 271 cxx_header = "dev/arm/rtc_pl031.hh" 272 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 273 amba_id = 0x00341031 274 275class Pl050(AmbaIntDevice): 276 type = 'Pl050' 277 cxx_header = "dev/arm/kmi.hh" 278 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 279 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 280 int_delay = '1us' 281 amba_id = 0x00141050 282 283class Pl111(AmbaDmaDevice): 284 type = 'Pl111' 285 cxx_header = "dev/arm/pl111.hh" 286 pixel_clock = Param.Clock('24MHz', "Pixel clock") 287 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 288 amba_id = 0x00141111 289 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 290 291class HDLcd(AmbaDmaDevice): 292 type = 'HDLcd' 293 cxx_header = "dev/arm/hdlcd.hh" 294 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 295 "display") 296 amba_id = 0x00141000 297 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 298 "selector order in some kernels") 299 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 300 "DMA line count (off by 1)") 301 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 302 303 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 304 305 pxl_clk = Param.ClockDomain("Pixel clock source") 306 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 307 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 308 "in KVM mode") 309 310class RealView(Platform): 311 type = 'RealView' 312 cxx_header = "dev/arm/realview.hh" 313 system = Param.System(Parent.any, "system") 314 _mem_regions = [(Addr(0), Addr('256MB'))] 315 316 def _on_chip_devices(self): 317 return [] 318 319 def _off_chip_devices(self): 320 return [] 321 322 _off_chip_ranges = [] 323 324 def _attach_device(self, device, bus, dma_ports=None): 325 if hasattr(device, "pio"): 326 device.pio = bus.master 327 if hasattr(device, "dma"): 328 if dma_ports is None: 329 device.dma = bus.slave 330 else: 331 dma_ports.append(device.dma) 332 333 def _attach_io(self, devices, *args, **kwargs): 334 for d in devices: 335 self._attach_device(d, *args, **kwargs) 336 337 def _attach_clk(self, devices, clkdomain): 338 for d in devices: 339 if hasattr(d, "clk_domain"): 340 d.clk_domain = clkdomain 341 342 def attachPciDevices(self): 343 pass 344 345 def enableMSIX(self): 346 pass 347 348 def onChipIOClkDomain(self, clkdomain): 349 self._attach_clk(self._on_chip_devices(), clkdomain) 350 351 def offChipIOClkDomain(self, clkdomain): 352 self._attach_clk(self._off_chip_devices(), clkdomain) 353 354 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 355 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 356 if bridge: 357 bridge.ranges = self._off_chip_ranges 358 359 def attachIO(self, *args, **kwargs): 360 self._attach_io(self._off_chip_devices(), *args, **kwargs) 361 362 def setupBootLoader(self, mem_bus, cur_sys, loc): 363 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 364 conf_table_reported = False) 365 self.nvmem.port = mem_bus.master 366 cur_sys.boot_loader = loc('boot.arm') 367 cur_sys.atags_addr = 0x100 368 cur_sys.load_addr_mask = 0xfffffff 369 cur_sys.load_offset = 0 370 371 372# Reference for memory map and interrupt number 373# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 374# Chapter 4: Programmer's Reference 375class RealViewPBX(RealView): 376 uart = Pl011(pio_addr=0x10009000, int_num=44) 377 realview_io = RealViewCtrl(pio_addr=0x10000000) 378 mcc = VExpressMCC() 379 dcc = CoreTile2A15DCC() 380 gic = Pl390() 381 pci_host = GenericPciHost( 382 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 383 pci_pio_base=0) 384 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 385 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 386 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 387 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 388 pio_addr=0x1f000600) 389 clcd = Pl111(pio_addr=0x10020000, int_num=55) 390 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 391 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 392 a9scu = A9SCU(pio_addr=0x1f000000) 393 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 394 io_shift = 1, ctrl_offset = 2, Command = 0x1, 395 BAR0 = 0x18000000, BAR0Size = '16B', 396 BAR1 = 0x18000100, BAR1Size = '1B', 397 BAR0LegacyIO = True, BAR1LegacyIO = True) 398 399 400 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 401 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 402 fake_mem=True) 403 dmac_fake = AmbaFake(pio_addr=0x10030000) 404 uart1_fake = AmbaFake(pio_addr=0x1000a000) 405 uart2_fake = AmbaFake(pio_addr=0x1000b000) 406 uart3_fake = AmbaFake(pio_addr=0x1000c000) 407 smc_fake = AmbaFake(pio_addr=0x100e1000) 408 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 409 watchdog_fake = AmbaFake(pio_addr=0x10010000) 410 gpio0_fake = AmbaFake(pio_addr=0x10013000) 411 gpio1_fake = AmbaFake(pio_addr=0x10014000) 412 gpio2_fake = AmbaFake(pio_addr=0x10015000) 413 ssp_fake = AmbaFake(pio_addr=0x1000d000) 414 sci_fake = AmbaFake(pio_addr=0x1000e000) 415 aaci_fake = AmbaFake(pio_addr=0x10004000) 416 mmc_fake = AmbaFake(pio_addr=0x10005000) 417 rtc = PL031(pio_addr=0x10017000, int_num=42) 418 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 419 420 421 # Attach I/O devices that are on chip and also set the appropriate 422 # ranges for the bridge 423 def attachOnChipIO(self, bus, bridge): 424 self.gic.pio = bus.master 425 self.l2x0_fake.pio = bus.master 426 self.a9scu.pio = bus.master 427 self.global_timer.pio = bus.master 428 self.local_cpu_timer.pio = bus.master 429 # Bridge ranges based on excluding what is part of on-chip I/O 430 # (gic, l2x0, a9scu, local_cpu_timer) 431 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 432 self.a9scu.pio_addr - 1), 433 AddrRange(self.flash_fake.pio_addr, 434 self.flash_fake.pio_addr + \ 435 self.flash_fake.pio_size - 1)] 436 437 # Set the clock domain for IO objects that are considered 438 # to be "close" to the cores. 439 def onChipIOClkDomain(self, clkdomain): 440 self.gic.clk_domain = clkdomain 441 self.l2x0_fake.clk_domain = clkdomain 442 self.a9scu.clkdomain = clkdomain 443 self.local_cpu_timer.clk_domain = clkdomain 444 445 # Attach I/O devices to specified bus object. Can't do this 446 # earlier, since the bus object itself is typically defined at the 447 # System level. 448 def attachIO(self, bus): 449 self.uart.pio = bus.master 450 self.realview_io.pio = bus.master 451 self.pci_host.pio = bus.master 452 self.timer0.pio = bus.master 453 self.timer1.pio = bus.master 454 self.clcd.pio = bus.master 455 self.clcd.dma = bus.slave 456 self.kmi0.pio = bus.master 457 self.kmi1.pio = bus.master 458 self.cf_ctrl.pio = bus.master 459 self.cf_ctrl.dma = bus.slave 460 self.dmac_fake.pio = bus.master 461 self.uart1_fake.pio = bus.master 462 self.uart2_fake.pio = bus.master 463 self.uart3_fake.pio = bus.master 464 self.smc_fake.pio = bus.master 465 self.sp810_fake.pio = bus.master 466 self.watchdog_fake.pio = bus.master 467 self.gpio0_fake.pio = bus.master 468 self.gpio1_fake.pio = bus.master 469 self.gpio2_fake.pio = bus.master 470 self.ssp_fake.pio = bus.master 471 self.sci_fake.pio = bus.master 472 self.aaci_fake.pio = bus.master 473 self.mmc_fake.pio = bus.master 474 self.rtc.pio = bus.master 475 self.flash_fake.pio = bus.master 476 self.energy_ctrl.pio = bus.master 477 478 # Set the clock domain for IO objects that are considered 479 # to be "far" away from the cores. 480 def offChipIOClkDomain(self, clkdomain): 481 self.uart.clk_domain = clkdomain 482 self.realview_io.clk_domain = clkdomain 483 self.timer0.clk_domain = clkdomain 484 self.timer1.clk_domain = clkdomain 485 self.clcd.clk_domain = clkdomain 486 self.kmi0.clk_domain = clkdomain 487 self.kmi1.clk_domain = clkdomain 488 self.cf_ctrl.clk_domain = clkdomain 489 self.dmac_fake.clk_domain = clkdomain 490 self.uart1_fake.clk_domain = clkdomain 491 self.uart2_fake.clk_domain = clkdomain 492 self.uart3_fake.clk_domain = clkdomain 493 self.smc_fake.clk_domain = clkdomain 494 self.sp810_fake.clk_domain = clkdomain 495 self.watchdog_fake.clk_domain = clkdomain 496 self.gpio0_fake.clk_domain = clkdomain 497 self.gpio1_fake.clk_domain = clkdomain 498 self.gpio2_fake.clk_domain = clkdomain 499 self.ssp_fake.clk_domain = clkdomain 500 self.sci_fake.clk_domain = clkdomain 501 self.aaci_fake.clk_domain = clkdomain 502 self.mmc_fake.clk_domain = clkdomain 503 self.rtc.clk_domain = clkdomain 504 self.flash_fake.clk_domain = clkdomain 505 self.energy_ctrl.clk_domain = clkdomain 506 507# Reference for memory map and interrupt number 508# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 509# Chapter 4: Programmer's Reference 510class RealViewEB(RealView): 511 uart = Pl011(pio_addr=0x10009000, int_num=44) 512 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 513 mcc = VExpressMCC() 514 dcc = CoreTile2A15DCC() 515 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 516 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 517 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 518 clcd = Pl111(pio_addr=0x10020000, int_num=23) 519 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 520 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 521 522 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 523 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 524 fake_mem=True) 525 dmac_fake = AmbaFake(pio_addr=0x10030000) 526 uart1_fake = AmbaFake(pio_addr=0x1000a000) 527 uart2_fake = AmbaFake(pio_addr=0x1000b000) 528 uart3_fake = AmbaFake(pio_addr=0x1000c000) 529 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 530 smc_fake = AmbaFake(pio_addr=0x100e1000) 531 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 532 watchdog_fake = AmbaFake(pio_addr=0x10010000) 533 gpio0_fake = AmbaFake(pio_addr=0x10013000) 534 gpio1_fake = AmbaFake(pio_addr=0x10014000) 535 gpio2_fake = AmbaFake(pio_addr=0x10015000) 536 ssp_fake = AmbaFake(pio_addr=0x1000d000) 537 sci_fake = AmbaFake(pio_addr=0x1000e000) 538 aaci_fake = AmbaFake(pio_addr=0x10004000) 539 mmc_fake = AmbaFake(pio_addr=0x10005000) 540 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 541 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 542 543 # Attach I/O devices that are on chip and also set the appropriate 544 # ranges for the bridge 545 def attachOnChipIO(self, bus, bridge): 546 self.gic.pio = bus.master 547 self.l2x0_fake.pio = bus.master 548 # Bridge ranges based on excluding what is part of on-chip I/O 549 # (gic, l2x0) 550 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 551 self.gic.cpu_addr - 1), 552 AddrRange(self.flash_fake.pio_addr, Addr.max)] 553 554 # Set the clock domain for IO objects that are considered 555 # to be "close" to the cores. 556 def onChipIOClkDomain(self, clkdomain): 557 self.gic.clk_domain = clkdomain 558 self.l2x0_fake.clk_domain = clkdomain 559 560 # Attach I/O devices to specified bus object. Can't do this 561 # earlier, since the bus object itself is typically defined at the 562 # System level. 563 def attachIO(self, bus): 564 self.uart.pio = bus.master 565 self.realview_io.pio = bus.master 566 self.pci_host.pio = bus.master 567 self.timer0.pio = bus.master 568 self.timer1.pio = bus.master 569 self.clcd.pio = bus.master 570 self.clcd.dma = bus.slave 571 self.kmi0.pio = bus.master 572 self.kmi1.pio = bus.master 573 self.dmac_fake.pio = bus.master 574 self.uart1_fake.pio = bus.master 575 self.uart2_fake.pio = bus.master 576 self.uart3_fake.pio = bus.master 577 self.smc_fake.pio = bus.master 578 self.sp810_fake.pio = bus.master 579 self.watchdog_fake.pio = bus.master 580 self.gpio0_fake.pio = bus.master 581 self.gpio1_fake.pio = bus.master 582 self.gpio2_fake.pio = bus.master 583 self.ssp_fake.pio = bus.master 584 self.sci_fake.pio = bus.master 585 self.aaci_fake.pio = bus.master 586 self.mmc_fake.pio = bus.master 587 self.rtc_fake.pio = bus.master 588 self.flash_fake.pio = bus.master 589 self.smcreg_fake.pio = bus.master 590 self.energy_ctrl.pio = bus.master 591 592 # Set the clock domain for IO objects that are considered 593 # to be "far" away from the cores. 594 def offChipIOClkDomain(self, clkdomain): 595 self.uart.clk_domain = clkdomain 596 self.realview_io.clk_domain = clkdomain 597 self.timer0.clk_domain = clkdomain 598 self.timer1.clk_domain = clkdomain 599 self.clcd.clk_domain = clkdomain 600 self.kmi0.clk_domain = clkdomain 601 self.kmi1.clk_domain = clkdomain 602 self.dmac_fake.clk_domain = clkdomain 603 self.uart1_fake.clk_domain = clkdomain 604 self.uart2_fake.clk_domain = clkdomain 605 self.uart3_fake.clk_domain = clkdomain 606 self.smc_fake.clk_domain = clkdomain 607 self.sp810_fake.clk_domain = clkdomain 608 self.watchdog_fake.clk_domain = clkdomain 609 self.gpio0_fake.clk_domain = clkdomain 610 self.gpio1_fake.clk_domain = clkdomain 611 self.gpio2_fake.clk_domain = clkdomain 612 self.ssp_fake.clk_domain = clkdomain 613 self.sci_fake.clk_domain = clkdomain 614 self.aaci_fake.clk_domain = clkdomain 615 self.mmc_fake.clk_domain = clkdomain 616 self.rtc.clk_domain = clkdomain 617 self.flash_fake.clk_domain = clkdomain 618 self.smcreg_fake.clk_domain = clkdomain 619 self.energy_ctrl.clk_domain = clkdomain 620 621class VExpress_EMM(RealView): 622 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 623 624 # Ranges based on excluding what is part of on-chip I/O (gic, 625 # a9scu) 626 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 627 AddrRange(0x30000000, size='256MB'), 628 AddrRange(0x40000000, size='512MB'), 629 AddrRange(0x18000000, size='64MB'), 630 AddrRange(0x1C000000, size='64MB')] 631 632 # Platform control device (off-chip) 633 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 634 idreg=0x02250000, pio_addr=0x1C010000) 635 636 mcc = VExpressMCC() 637 dcc = CoreTile2A15DCC() 638 639 ### On-chip devices ### 640 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 641 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 642 643 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 644 pio_addr=0x2C080000) 645 646 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 647 pio_addr=0x2b000000, int_num=117, 648 workaround_swap_rb=True) 649 650 def _on_chip_devices(self): 651 devices = [ 652 self.gic, self.vgic, 653 self.local_cpu_timer 654 ] 655 if hasattr(self, "gicv2m"): 656 devices.append(self.gicv2m) 657 devices.append(self.hdlcd) 658 return devices 659 660 ### Off-chip devices ### 661 uart = Pl011(pio_addr=0x1c090000, int_num=37) 662 pci_host = GenericPciHost( 663 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 664 pci_pio_base=0) 665 666 generic_timer = GenericTimer(int_phys=29, int_virt=27) 667 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 668 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 669 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 670 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 671 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 672 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 673 io_shift = 2, ctrl_offset = 2, Command = 0x1, 674 BAR0 = 0x1C1A0000, BAR0Size = '256B', 675 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 676 BAR0LegacyIO = True, BAR1LegacyIO = True) 677 678 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 679 conf_table_reported = False) 680 rtc = PL031(pio_addr=0x1C170000, int_num=36) 681 682 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 683 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 684 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 685 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 686 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 687 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 688 aaci_fake = AmbaFake(pio_addr=0x1C040000) 689 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 690 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 691 mmc_fake = AmbaFake(pio_addr=0x1c050000) 692 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 693 694 def _off_chip_devices(self): 695 devices = [ 696 self.uart, 697 self.realview_io, 698 self.pci_host, 699 self.timer0, 700 self.timer1, 701 self.clcd, 702 self.kmi0, 703 self.kmi1, 704 self.cf_ctrl, 705 self.rtc, 706 self.vram, 707 self.l2x0_fake, 708 self.uart1_fake, 709 self.uart2_fake, 710 self.uart3_fake, 711 self.sp810_fake, 712 self.watchdog_fake, 713 self.aaci_fake, 714 self.lan_fake, 715 self.usb_fake, 716 self.mmc_fake, 717 self.energy_ctrl, 718 ] 719 # Try to attach the I/O if it exists 720 if hasattr(self, "ide"): 721 devices.append(self.ide) 722 if hasattr(self, "ethernet"): 723 devices.append(self.ethernet) 724 return devices 725 726 # Attach any PCI devices that are supported 727 def attachPciDevices(self): 728 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 729 InterruptLine=1, InterruptPin=1) 730 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 731 InterruptLine=2, InterruptPin=2) 732 733 def enableMSIX(self): 734 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 735 self.gicv2m = Gicv2m() 736 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 737 738 def setupBootLoader(self, mem_bus, cur_sys, loc): 739 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 740 conf_table_reported = False) 741 self.nvmem.port = mem_bus.master 742 if not cur_sys.boot_loader: 743 cur_sys.boot_loader = loc('boot_emm.arm') 744 cur_sys.atags_addr = 0x8000000 745 cur_sys.load_addr_mask = 0xfffffff 746 cur_sys.load_offset = 0x80000000 747 748class VExpress_EMM64(VExpress_EMM): 749 # Three memory regions are specified totalling 512GB 750 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 751 (Addr('512GB'), Addr('480GB'))] 752 pci_host = GenericPciHost( 753 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 754 pci_pio_base=0x2f000000) 755 756 def setupBootLoader(self, mem_bus, cur_sys, loc): 757 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 758 conf_table_reported=False) 759 self.nvmem.port = mem_bus.master 760 if not cur_sys.boot_loader: 761 cur_sys.boot_loader = loc('boot_emm.arm64') 762 cur_sys.atags_addr = 0x8000000 763 cur_sys.load_addr_mask = 0xfffffff 764 cur_sys.load_offset = 0x80000000 765 766 767class VExpress_GEM5_V1(RealView): 768 """ 769The VExpress gem5 memory map is loosely based on a modified 770Versatile Express RS1 memory map. 771 772The gem5 platform has been designed to implement a subset of the 773original Versatile Express RS1 memory map. Off-chip peripherals should, 774when possible, adhere to the Versatile Express memory map. Non-PCI 775off-chip devices that are gem5-specific should live in the CS5 memory 776space to avoid conflicts with existing devices that we might want to 777model in the future. Such devices should normally have interrupts in 778the gem5-specific SPI range. 779 780On-chip peripherals are loosely modeled after the ARM CoreTile Express 781A15x2 A7x3 memory and interrupt map. In particular, the GIC and 782Generic Timer have the same interrupt lines and base addresses. Other 783on-chip devices are gem5 specific. 784 785Unlike the original Versatile Express RS2 extended platform, gem5 implements a 786large contigious DRAM space, without aliases or holes, starting at the 7872GiB boundary. This means that PCI memory is limited to 1GiB. 788 789Memory map: 790 0x00000000-0x03ffffff: Boot memory (CS0) 791 0x04000000-0x07ffffff: Reserved 792 0x08000000-0x0bffffff: Reserved (CS0 alias) 793 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 794 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 795 0x10000000-0x1000ffff: gem5 energy controller 796 0x10010000-0x1001ffff: gem5 pseudo-ops 797 798 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 799 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 800 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 801 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 802 0x1c060000-0x1c06ffff: KMI0 (keyboard) 803 0x1c070000-0x1c07ffff: KMI1 (mouse) 804 0x1c090000-0x1c09ffff: UART0 805 0x1c0a0000-0x1c0affff: UART1 (reserved) 806 0x1c0b0000-0x1c0bffff: UART2 (reserved) 807 0x1c0c0000-0x1c0cffff: UART3 (reserved) 808 0x1c170000-0x1c17ffff: RTC 809 810 0x20000000-0x3fffffff: On-chip peripherals: 811 0x2b000000-0x2b00ffff: HDLCD 812 813 0x2c001000-0x2c001fff: GIC (distributor) 814 0x2c002000-0x2c0020ff: GIC (CPU interface) 815 0x2c004000-0x2c005fff: vGIC (HV) 816 0x2c006000-0x2c007fff: vGIC (VCPU) 817 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 818 819 0x2d000000-0x2d00ffff: GPU (reserved) 820 821 0x2f000000-0x2fffffff: PCI IO space 822 0x30000000-0x3fffffff: PCI config space 823 824 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 825 826 0x80000000-X: DRAM 827 828Interrupts: 829 0- 15: Software generated interrupts (SGIs) 830 16- 31: On-chip private peripherals (PPIs) 831 25 : vgic 832 26 : generic_timer (hyp) 833 27 : generic_timer (virt) 834 28 : Reserved (Legacy FIQ) 835 29 : generic_timer (phys, sec) 836 30 : generic_timer (phys, non-sec) 837 31 : Reserved (Legacy IRQ) 838 32- 95: Mother board peripherals (SPIs) 839 32 : Reserved (SP805) 840 33 : Reserved (IOFPGA SW int) 841 34-35: Reserved (SP804) 842 36 : RTC 843 37-40: uart0-uart3 844 41-42: Reserved (PL180) 845 43 : Reserved (AACI) 846 44-45: kmi0-kmi1 847 46 : Reserved (CLCD) 848 47 : Reserved (Ethernet) 849 48 : Reserved (USB) 850 95-255: On-chip interrupt sources (we use these for 851 gem5-specific devices, SPIs) 852 95 : HDLCD 853 96- 98: GPU (reserved) 854 100-103: PCI 855 256-319: MSI frame 0 (gem5-specific, SPIs) 856 320-511: Unused 857 858 """ 859 860 # Everything above 2GiB is memory 861 _mem_regions = [(Addr('2GB'), Addr('510GB'))] 862 863 _off_chip_ranges = [ 864 # CS1-CS5 865 AddrRange(0x0c000000, 0x1fffffff), 866 # External AXI interface (PCI) 867 AddrRange(0x2f000000, 0x7fffffff), 868 ] 869 870 # Platform control device (off-chip) 871 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 872 idreg=0x02250000, pio_addr=0x1c010000) 873 mcc = VExpressMCC() 874 dcc = CoreTile2A15DCC() 875 876 ### On-chip devices ### 877 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 878 it_lines=512) 879 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 880 gicv2m = Gicv2m() 881 gicv2m.frames = [ 882 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 883 ] 884 885 generic_timer = GenericTimer(int_phys=29, int_virt=27) 886 887 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 888 pio_addr=0x2b000000, int_num=95) 889 890 def _on_chip_devices(self): 891 return [ 892 self.gic, self.vgic, self.gicv2m, 893 self.hdlcd, 894 self.generic_timer, 895 ] 896 897 ### Off-chip devices ### 898 uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 899 900 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 901 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 902 903 rtc = PL031(pio_addr=0x1c170000, int_num=36) 904 905 ### gem5-specific off-chip devices ### 906 pci_host = GenericArmPciHost( 907 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 908 pci_pio_base=0x2f000000, 909 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 910 911 energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 912 913 914 def _off_chip_devices(self): 915 return [ 916 self.realview_io, 917 self.uart0, 918 self.kmi0, self.kmi1, 919 self.rtc, 920 self.pci_host, 921 self.energy_ctrl, 922 ] 923 924 def attachPciDevice(self, device, *args, **kwargs): 925 device.host = self.pci_host 926 self._attach_device(device, *args, **kwargs) 927 928 def setupBootLoader(self, mem_bus, cur_sys, loc): 929 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 930 conf_table_reported=False) 931 self.nvmem.port = mem_bus.master 932 if not cur_sys.boot_loader: 933 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 934 cur_sys.atags_addr = 0x8000000 935 # the old load_add_mask 0xfffffff works for 32-bit kernel 936 # but not the 64-bit one. The new value 0x7ffffff works for both 937 cur_sys.load_addr_mask = 0x7ffffff 938 cur_sys.load_offset = 0x80000000 939 940 # Setup m5ops. It's technically not a part of the boot 941 # loader, but this is the only place we can configure the 942 # system. 943 cur_sys.m5ops_base = 0x10010000 944