tsunami_pchip.cc revision 775 
14484Sbinkertn@umich.edu/* $Id$ */
24484Sbinkertn@umich.edu
34484Sbinkertn@umich.edu/* @file
44484Sbinkertn@umich.edu * Tsunami PChip (pci)
54484Sbinkertn@umich.edu */
64484Sbinkertn@umich.edu
74484Sbinkertn@umich.edu#include <deque>
84484Sbinkertn@umich.edu#include <string>
94484Sbinkertn@umich.edu#include <vector>
104484Sbinkertn@umich.edu
114484Sbinkertn@umich.edu#include "base/trace.hh"
124484Sbinkertn@umich.edu#include "cpu/exec_context.hh"
134484Sbinkertn@umich.edu#include "dev/console.hh"
144484Sbinkertn@umich.edu#include "dev/etherdev.hh"
154484Sbinkertn@umich.edu#include "dev/scsi_ctrl.hh"
164484Sbinkertn@umich.edu#include "dev/tlaser_clock.hh"
174484Sbinkertn@umich.edu#include "dev/tsunami_pchip.hh"
184484Sbinkertn@umich.edu#include "dev/tsunamireg.h"
194484Sbinkertn@umich.edu#include "dev/tsunami.hh"
204484Sbinkertn@umich.edu#include "mem/functional_mem/memory_control.hh"
214484Sbinkertn@umich.edu#include "sim/builder.hh"
224484Sbinkertn@umich.edu#include "sim/system.hh"
234484Sbinkertn@umich.edu
244484Sbinkertn@umich.eduusing namespace std;
254484Sbinkertn@umich.edu
264484Sbinkertn@umich.eduTsunamiPChip::TsunamiPChip(const string &name, Tsunami *t,
274484Sbinkertn@umich.edu                       Addr addr, Addr mask, MemoryController *mmu)
284484Sbinkertn@umich.edu    : MmapDevice(name, addr, mask, mmu), tsunami(t)
294484Sbinkertn@umich.edu{
304484Sbinkertn@umich.edu    wsba0 = 0;
314484Sbinkertn@umich.edu    wsba1 = 0;
324484Sbinkertn@umich.edu    wsba2 = 0;
334484Sbinkertn@umich.edu    wsba3 = 0;
344484Sbinkertn@umich.edu    wsm0 = 0;
354484Sbinkertn@umich.edu    wsm1 = 0;
364484Sbinkertn@umich.edu    wsm2 = 0;
374484Sbinkertn@umich.edu    wsm3 = 0;
384484Sbinkertn@umich.edu    tba0 = 0;
394484Sbinkertn@umich.edu    tba1 = 0;
404484Sbinkertn@umich.edu    tba2 = 0;
414484Sbinkertn@umich.edu    tba3 = 0;
424484Sbinkertn@umich.edu
434484Sbinkertn@umich.edu    //Set back pointer in tsunami
444484Sbinkertn@umich.edu    tsunami->pchip = this;
454484Sbinkertn@umich.edu}
464484Sbinkertn@umich.edu
474484Sbinkertn@umich.eduFault
484484Sbinkertn@umich.eduTsunamiPChip::read(MemReqPtr req, uint8_t *data)
494484Sbinkertn@umich.edu{
504484Sbinkertn@umich.edu    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
514484Sbinkertn@umich.edu            req->vaddr, req->size);
524484Sbinkertn@umich.edu
534484Sbinkertn@umich.edu    Addr daddr = (req->paddr & addr_mask) >> 6;
544484Sbinkertn@umich.edu//    ExecContext *xc = req->xc;
554484Sbinkertn@umich.edu//    int cpuid = xc->cpu_id;
564484Sbinkertn@umich.edu
574484Sbinkertn@umich.edu    switch (req->size) {
584484Sbinkertn@umich.edu
594484Sbinkertn@umich.edu      case sizeof(uint64_t):
604484Sbinkertn@umich.edu          switch(daddr) {
614484Sbinkertn@umich.edu              case TSDEV_PC_WSBA0:
624484Sbinkertn@umich.edu                    *(uint64_t*)data = wsba0;
634484Sbinkertn@umich.edu                    return No_Fault;
644484Sbinkertn@umich.edu              case TSDEV_PC_WSBA1:
654484Sbinkertn@umich.edu                    *(uint64_t*)data = wsba1;
664484Sbinkertn@umich.edu                    return No_Fault;
674484Sbinkertn@umich.edu              case TSDEV_PC_WSBA2:
684484Sbinkertn@umich.edu                    *(uint64_t*)data = wsba2;
694484Sbinkertn@umich.edu                    return No_Fault;
704484Sbinkertn@umich.edu              case TSDEV_PC_WSBA3:
714484Sbinkertn@umich.edu                    *(uint64_t*)data = wsba3;
724484Sbinkertn@umich.edu                    return No_Fault;
734484Sbinkertn@umich.edu              case TSDEV_PC_WSM0:
744484Sbinkertn@umich.edu                    *(uint64_t*)data = wsm0;
754484Sbinkertn@umich.edu                    return No_Fault;
764484Sbinkertn@umich.edu              case TSDEV_PC_WSM1:
774484Sbinkertn@umich.edu                    *(uint64_t*)data = wsm1;
784484Sbinkertn@umich.edu                    return No_Fault;
794484Sbinkertn@umich.edu              case TSDEV_PC_WSM2:
804484Sbinkertn@umich.edu                    *(uint64_t*)data = wsm2;
814484Sbinkertn@umich.edu                    return No_Fault;
824484Sbinkertn@umich.edu              case TSDEV_PC_WSM3:
834484Sbinkertn@umich.edu                    *(uint64_t*)data = wsm3;
844484Sbinkertn@umich.edu                    return No_Fault;
854484Sbinkertn@umich.edu              case TSDEV_PC_TBA0:
864484Sbinkertn@umich.edu                    *(uint64_t*)data = tba0;
874484Sbinkertn@umich.edu                    return No_Fault;
884484Sbinkertn@umich.edu              case TSDEV_PC_TBA1:
894484Sbinkertn@umich.edu                    *(uint64_t*)data = tba1;
904484Sbinkertn@umich.edu                    return No_Fault;
914484Sbinkertn@umich.edu              case TSDEV_PC_TBA2:
924484Sbinkertn@umich.edu                    *(uint64_t*)data = tba2;
934484Sbinkertn@umich.edu                    return No_Fault;
944484Sbinkertn@umich.edu              case TSDEV_PC_TBA3:
954484Sbinkertn@umich.edu                    *(uint64_t*)data = tba3;
964484Sbinkertn@umich.edu                    return No_Fault;
974484Sbinkertn@umich.edu              case TSDEV_PC_PCTL:
984484Sbinkertn@umich.edu                    // might want to change the clock??
994484Sbinkertn@umich.edu                    *(uint64_t*)data = 0x00; // try this
1004484Sbinkertn@umich.edu                    return No_Fault;
1014484Sbinkertn@umich.edu              case TSDEV_PC_PLAT:
1024484Sbinkertn@umich.edu                    panic("PC_PLAT not implemented\n");
1034484Sbinkertn@umich.edu              case TSDEV_PC_RES:
1044484Sbinkertn@umich.edu                    panic("PC_RES not implemented\n");
1054484Sbinkertn@umich.edu              case TSDEV_PC_PERROR:
1064484Sbinkertn@umich.edu                    panic("PC_PERROR not implemented\n");
1074484Sbinkertn@umich.edu              case TSDEV_PC_PERRMASK:
1084484Sbinkertn@umich.edu                    panic("PC_PERRMASK not implemented\n");
1094484Sbinkertn@umich.edu              case TSDEV_PC_PERRSET:
1104484Sbinkertn@umich.edu                    panic("PC_PERRSET not implemented\n");
1114484Sbinkertn@umich.edu              case TSDEV_PC_TLBIV:
1124484Sbinkertn@umich.edu                    panic("PC_TLBIV not implemented\n");
1134484Sbinkertn@umich.edu              case TSDEV_PC_TLBIA:
1144484Sbinkertn@umich.edu                    *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
1154484Sbinkertn@umich.edu                    return No_Fault;
1164484Sbinkertn@umich.edu              case TSDEV_PC_PMONCTL:
1174484Sbinkertn@umich.edu                    panic("PC_PMONCTL not implemented\n");
1184484Sbinkertn@umich.edu              case TSDEV_PC_PMONCNT:
1194484Sbinkertn@umich.edu                    panic("PC_PMONCTN not implemented\n");
1204484Sbinkertn@umich.edu              default:
1214484Sbinkertn@umich.edu                  panic("Default in PChip Read reached reading 0x%x\n", daddr);
1224484Sbinkertn@umich.edu
1234484Sbinkertn@umich.edu           } // uint64_t
1244484Sbinkertn@umich.edu
1254484Sbinkertn@umich.edu      break;
1264484Sbinkertn@umich.edu      case sizeof(uint32_t):
1274484Sbinkertn@umich.edu      case sizeof(uint16_t):
1284484Sbinkertn@umich.edu      case sizeof(uint8_t):
1294484Sbinkertn@umich.edu      default:
1304484Sbinkertn@umich.edu        panic("invalid access size(?) for tsunami register!\n\n");
1314484Sbinkertn@umich.edu    }
1324484Sbinkertn@umich.edu    DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
1334484Sbinkertn@umich.edu
1344484Sbinkertn@umich.edu    return No_Fault;
1354484Sbinkertn@umich.edu}
1364484Sbinkertn@umich.edu
1374484Sbinkertn@umich.eduFault
1384484Sbinkertn@umich.eduTsunamiPChip::write(MemReqPtr req, const uint8_t *data)
1394484Sbinkertn@umich.edu{
1404484Sbinkertn@umich.edu    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
1414484Sbinkertn@umich.edu            req->vaddr, req->size);
1424484Sbinkertn@umich.edu
1434484Sbinkertn@umich.edu    Addr daddr = (req->paddr & addr_mask) >> 6;
1444484Sbinkertn@umich.edu
1454484Sbinkertn@umich.edu    switch (req->size) {
1464484Sbinkertn@umich.edu
1474484Sbinkertn@umich.edu      case sizeof(uint64_t):
1484484Sbinkertn@umich.edu          switch(daddr) {
1494484Sbinkertn@umich.edu              case TSDEV_PC_WSBA0:
1504484Sbinkertn@umich.edu                    wsba0 = *(uint64_t*)data;
1514484Sbinkertn@umich.edu                    return No_Fault;
152              case TSDEV_PC_WSBA1:
153                    wsba1 = *(uint64_t*)data;
154                    return No_Fault;
155              case TSDEV_PC_WSBA2:
156                    wsba2 = *(uint64_t*)data;
157                    return No_Fault;
158              case TSDEV_PC_WSBA3:
159                    wsba3 = *(uint64_t*)data;
160                    return No_Fault;
161              case TSDEV_PC_WSM0:
162                    wsm0 = *(uint64_t*)data;
163                    return No_Fault;
164              case TSDEV_PC_WSM1:
165                    wsm1 = *(uint64_t*)data;
166                    return No_Fault;
167              case TSDEV_PC_WSM2:
168                    wsm2 = *(uint64_t*)data;
169                    return No_Fault;
170              case TSDEV_PC_WSM3:
171                    wsm3 = *(uint64_t*)data;
172                    return No_Fault;
173              case TSDEV_PC_TBA0:
174                    tba0 = *(uint64_t*)data;
175                    return No_Fault;
176              case TSDEV_PC_TBA1:
177                    tba1 = *(uint64_t*)data;
178                    return No_Fault;
179              case TSDEV_PC_TBA2:
180                    tba2 = *(uint64_t*)data;
181                    return No_Fault;
182              case TSDEV_PC_TBA3:
183                    tba3 = *(uint64_t*)data;
184                    return No_Fault;
185              case TSDEV_PC_PCTL:
186                    // might want to change the clock??
187                    //*(uint64_t*)data; // try this
188                    return No_Fault;
189              case TSDEV_PC_PLAT:
190                    panic("PC_PLAT not implemented\n");
191              case TSDEV_PC_RES:
192                    panic("PC_RES not implemented\n");
193              case TSDEV_PC_PERROR:
194                    panic("PC_PERROR not implemented\n");
195              case TSDEV_PC_PERRMASK:
196                    panic("PC_PERRMASK not implemented\n");
197              case TSDEV_PC_PERRSET:
198                    panic("PC_PERRSET not implemented\n");
199              case TSDEV_PC_TLBIV:
200                    panic("PC_TLBIV not implemented\n");
201              case TSDEV_PC_TLBIA:
202                    return No_Fault; // value ignored, supposted to invalidate SG TLB
203              case TSDEV_PC_PMONCTL:
204                    panic("PC_PMONCTL not implemented\n");
205              case TSDEV_PC_PMONCNT:
206                    panic("PC_PMONCTN not implemented\n");
207              default:
208                  panic("Default in PChip Read reached reading 0x%x\n", daddr);
209
210           } // uint64_t
211
212      break;
213      case sizeof(uint32_t):
214      case sizeof(uint16_t):
215      case sizeof(uint8_t):
216      default:
217        panic("invalid access size(?) for tsunami register!\n\n");
218    }
219
220    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
221
222    return No_Fault;
223}
224
225void
226TsunamiPChip::serialize(std::ostream &os)
227{
228    // code should be written
229}
230
231void
232TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
233{
234    //code should be written
235}
236
237BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
238
239    SimObjectParam<Tsunami *> tsunami;
240    SimObjectParam<MemoryController *> mmu;
241    Param<Addr> addr;
242    Param<Addr> mask;
243
244END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
245
246BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
247
248    INIT_PARAM(tsunami, "Tsunami"),
249    INIT_PARAM(mmu, "Memory Controller"),
250    INIT_PARAM(addr, "Device Address"),
251    INIT_PARAM(mask, "Address Mask")
252
253END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
254
255CREATE_SIM_OBJECT(TsunamiPChip)
256{
257    return new TsunamiPChip(getInstanceName(), tsunami, addr, mask, mmu);
258}
259
260REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
261