tsunami_pchip.cc revision 775
13569Sgblack@eecs.umich.edu/* $Id$ */ 23569Sgblack@eecs.umich.edu 33569Sgblack@eecs.umich.edu/* @file 43569Sgblack@eecs.umich.edu * Tsunami PChip (pci) 53569Sgblack@eecs.umich.edu */ 63569Sgblack@eecs.umich.edu 73569Sgblack@eecs.umich.edu#include <deque> 83569Sgblack@eecs.umich.edu#include <string> 93569Sgblack@eecs.umich.edu#include <vector> 103569Sgblack@eecs.umich.edu 113569Sgblack@eecs.umich.edu#include "base/trace.hh" 123569Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 133569Sgblack@eecs.umich.edu#include "dev/console.hh" 143569Sgblack@eecs.umich.edu#include "dev/etherdev.hh" 153569Sgblack@eecs.umich.edu#include "dev/scsi_ctrl.hh" 163569Sgblack@eecs.umich.edu#include "dev/tlaser_clock.hh" 173569Sgblack@eecs.umich.edu#include "dev/tsunami_pchip.hh" 183569Sgblack@eecs.umich.edu#include "dev/tsunamireg.h" 193569Sgblack@eecs.umich.edu#include "dev/tsunami.hh" 203569Sgblack@eecs.umich.edu#include "mem/functional_mem/memory_control.hh" 213569Sgblack@eecs.umich.edu#include "sim/builder.hh" 223569Sgblack@eecs.umich.edu#include "sim/system.hh" 233569Sgblack@eecs.umich.edu 243569Sgblack@eecs.umich.eduusing namespace std; 253569Sgblack@eecs.umich.edu 263569Sgblack@eecs.umich.eduTsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, 273569Sgblack@eecs.umich.edu Addr addr, Addr mask, MemoryController *mmu) 283804Ssaidi@eecs.umich.edu : MmapDevice(name, addr, mask, mmu), tsunami(t) 293569Sgblack@eecs.umich.edu{ 303569Sgblack@eecs.umich.edu wsba0 = 0; 313918Ssaidi@eecs.umich.edu wsba1 = 0; 323918Ssaidi@eecs.umich.edu wsba2 = 0; 333804Ssaidi@eecs.umich.edu wsba3 = 0; 343811Ssaidi@eecs.umich.edu wsm0 = 0; 353569Sgblack@eecs.umich.edu wsm1 = 0; 363824Ssaidi@eecs.umich.edu wsm2 = 0; 373811Ssaidi@eecs.umich.edu wsm3 = 0; 383811Ssaidi@eecs.umich.edu tba0 = 0; 393823Ssaidi@eecs.umich.edu tba1 = 0; 403823Ssaidi@eecs.umich.edu tba2 = 0; 413823Ssaidi@eecs.umich.edu tba3 = 0; 424103Ssaidi@eecs.umich.edu 433569Sgblack@eecs.umich.edu //Set back pointer in tsunami 443804Ssaidi@eecs.umich.edu tsunami->pchip = this; 453804Ssaidi@eecs.umich.edu} 464088Sbinkertn@umich.edu 473569Sgblack@eecs.umich.eduFault 485034Smilesck@eecs.umich.eduTsunamiPChip::read(MemReqPtr req, uint8_t *data) 495358Sgblack@eecs.umich.edu{ 503881Ssaidi@eecs.umich.edu DPRINTF(Tsunami, "read va=%#x size=%d\n", 513804Ssaidi@eecs.umich.edu req->vaddr, req->size); 523804Ssaidi@eecs.umich.edu 533804Ssaidi@eecs.umich.edu Addr daddr = (req->paddr & addr_mask) >> 6; 545555Snate@binkert.org// ExecContext *xc = req->xc; 553569Sgblack@eecs.umich.edu// int cpuid = xc->cpu_id; 563804Ssaidi@eecs.umich.edu 573918Ssaidi@eecs.umich.edu switch (req->size) { 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu case sizeof(uint64_t): 603881Ssaidi@eecs.umich.edu switch(daddr) { 614990Sgblack@eecs.umich.edu case TSDEV_PC_WSBA0: 624990Sgblack@eecs.umich.edu *(uint64_t*)data = wsba0; 634990Sgblack@eecs.umich.edu return No_Fault; 644990Sgblack@eecs.umich.edu case TSDEV_PC_WSBA1: 654990Sgblack@eecs.umich.edu *(uint64_t*)data = wsba1; 664990Sgblack@eecs.umich.edu return No_Fault; 674990Sgblack@eecs.umich.edu case TSDEV_PC_WSBA2: 684990Sgblack@eecs.umich.edu *(uint64_t*)data = wsba2; 694990Sgblack@eecs.umich.edu return No_Fault; 706022Sgblack@eecs.umich.edu case TSDEV_PC_WSBA3: 716022Sgblack@eecs.umich.edu *(uint64_t*)data = wsba3; 726022Sgblack@eecs.umich.edu return No_Fault; 733804Ssaidi@eecs.umich.edu case TSDEV_PC_WSM0: 743569Sgblack@eecs.umich.edu *(uint64_t*)data = wsm0; 753804Ssaidi@eecs.umich.edu return No_Fault; 763804Ssaidi@eecs.umich.edu case TSDEV_PC_WSM1: 773804Ssaidi@eecs.umich.edu *(uint64_t*)data = wsm1; 783804Ssaidi@eecs.umich.edu return No_Fault; 793881Ssaidi@eecs.umich.edu case TSDEV_PC_WSM2: 803804Ssaidi@eecs.umich.edu *(uint64_t*)data = wsm2; 813804Ssaidi@eecs.umich.edu return No_Fault; 823804Ssaidi@eecs.umich.edu case TSDEV_PC_WSM3: 833804Ssaidi@eecs.umich.edu *(uint64_t*)data = wsm3; 843804Ssaidi@eecs.umich.edu return No_Fault; 853804Ssaidi@eecs.umich.edu case TSDEV_PC_TBA0: 863804Ssaidi@eecs.umich.edu *(uint64_t*)data = tba0; 873569Sgblack@eecs.umich.edu return No_Fault; 883569Sgblack@eecs.umich.edu case TSDEV_PC_TBA1: 893804Ssaidi@eecs.umich.edu *(uint64_t*)data = tba1; 903804Ssaidi@eecs.umich.edu return No_Fault; 913826Ssaidi@eecs.umich.edu case TSDEV_PC_TBA2: 923804Ssaidi@eecs.umich.edu *(uint64_t*)data = tba2; 933804Ssaidi@eecs.umich.edu return No_Fault; 943826Ssaidi@eecs.umich.edu case TSDEV_PC_TBA3: 953907Ssaidi@eecs.umich.edu *(uint64_t*)data = tba3; 963826Ssaidi@eecs.umich.edu return No_Fault; 973811Ssaidi@eecs.umich.edu case TSDEV_PC_PCTL: 983836Ssaidi@eecs.umich.edu // might want to change the clock?? 993915Ssaidi@eecs.umich.edu *(uint64_t*)data = 0x00; // try this 1003907Ssaidi@eecs.umich.edu return No_Fault; 1013881Ssaidi@eecs.umich.edu case TSDEV_PC_PLAT: 1023881Ssaidi@eecs.umich.edu panic("PC_PLAT not implemented\n"); 1033881Ssaidi@eecs.umich.edu case TSDEV_PC_RES: 1043881Ssaidi@eecs.umich.edu panic("PC_RES not implemented\n"); 1053907Ssaidi@eecs.umich.edu case TSDEV_PC_PERROR: 1063881Ssaidi@eecs.umich.edu panic("PC_PERROR not implemented\n"); 1075555Snate@binkert.org case TSDEV_PC_PERRMASK: 1085555Snate@binkert.org panic("PC_PERRMASK not implemented\n"); 1095555Snate@binkert.org case TSDEV_PC_PERRSET: 1103881Ssaidi@eecs.umich.edu panic("PC_PERRSET not implemented\n"); 1113881Ssaidi@eecs.umich.edu case TSDEV_PC_TLBIV: 1123907Ssaidi@eecs.umich.edu panic("PC_TLBIV not implemented\n"); 1133907Ssaidi@eecs.umich.edu case TSDEV_PC_TLBIA: 1143907Ssaidi@eecs.umich.edu *(uint64_t*)data = 0x00; // shouldn't be readable, but linux 1153907Ssaidi@eecs.umich.edu return No_Fault; 1163907Ssaidi@eecs.umich.edu case TSDEV_PC_PMONCTL: 1173907Ssaidi@eecs.umich.edu panic("PC_PMONCTL not implemented\n"); 1183907Ssaidi@eecs.umich.edu case TSDEV_PC_PMONCNT: 1193907Ssaidi@eecs.umich.edu panic("PC_PMONCTN not implemented\n"); 1203907Ssaidi@eecs.umich.edu default: 1213907Ssaidi@eecs.umich.edu panic("Default in PChip Read reached reading 0x%x\n", daddr); 1223907Ssaidi@eecs.umich.edu 1233907Ssaidi@eecs.umich.edu } // uint64_t 1243907Ssaidi@eecs.umich.edu 1253907Ssaidi@eecs.umich.edu break; 1263907Ssaidi@eecs.umich.edu case sizeof(uint32_t): 1273907Ssaidi@eecs.umich.edu case sizeof(uint16_t): 1283907Ssaidi@eecs.umich.edu case sizeof(uint8_t): 1293907Ssaidi@eecs.umich.edu default: 1303907Ssaidi@eecs.umich.edu panic("invalid access size(?) for tsunami register!\n\n"); 1313907Ssaidi@eecs.umich.edu } 1323907Ssaidi@eecs.umich.edu DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 1333907Ssaidi@eecs.umich.edu 1343881Ssaidi@eecs.umich.edu return No_Fault; 1353881Ssaidi@eecs.umich.edu} 1363881Ssaidi@eecs.umich.edu 1373881Ssaidi@eecs.umich.eduFault 1383881Ssaidi@eecs.umich.eduTsunamiPChip::write(MemReqPtr req, const uint8_t *data) 1393881Ssaidi@eecs.umich.edu{ 1403881Ssaidi@eecs.umich.edu DPRINTF(Tsunami, "write - va=%#x size=%d \n", 1413881Ssaidi@eecs.umich.edu req->vaddr, req->size); 1423881Ssaidi@eecs.umich.edu 1433881Ssaidi@eecs.umich.edu Addr daddr = (req->paddr & addr_mask) >> 6; 1443881Ssaidi@eecs.umich.edu 1453881Ssaidi@eecs.umich.edu switch (req->size) { 1463907Ssaidi@eecs.umich.edu 1473811Ssaidi@eecs.umich.edu case sizeof(uint64_t): 1483826Ssaidi@eecs.umich.edu switch(daddr) { 1493826Ssaidi@eecs.umich.edu case TSDEV_PC_WSBA0: 1503826Ssaidi@eecs.umich.edu wsba0 = *(uint64_t*)data; 1513826Ssaidi@eecs.umich.edu return No_Fault; 1523881Ssaidi@eecs.umich.edu case TSDEV_PC_WSBA1: 1533881Ssaidi@eecs.umich.edu wsba1 = *(uint64_t*)data; 1543881Ssaidi@eecs.umich.edu return No_Fault; 1553881Ssaidi@eecs.umich.edu case TSDEV_PC_WSBA2: 1563881Ssaidi@eecs.umich.edu wsba2 = *(uint64_t*)data; 1573881Ssaidi@eecs.umich.edu return No_Fault; 1583881Ssaidi@eecs.umich.edu case TSDEV_PC_WSBA3: 1593881Ssaidi@eecs.umich.edu wsba3 = *(uint64_t*)data; 1603881Ssaidi@eecs.umich.edu return No_Fault; 1613881Ssaidi@eecs.umich.edu case TSDEV_PC_WSM0: 1623881Ssaidi@eecs.umich.edu wsm0 = *(uint64_t*)data; 1633881Ssaidi@eecs.umich.edu return No_Fault; 1643881Ssaidi@eecs.umich.edu case TSDEV_PC_WSM1: 1653881Ssaidi@eecs.umich.edu wsm1 = *(uint64_t*)data; 1663881Ssaidi@eecs.umich.edu return No_Fault; 1673826Ssaidi@eecs.umich.edu case TSDEV_PC_WSM2: 1683826Ssaidi@eecs.umich.edu wsm2 = *(uint64_t*)data; 1693826Ssaidi@eecs.umich.edu return No_Fault; 1703826Ssaidi@eecs.umich.edu case TSDEV_PC_WSM3: 1713826Ssaidi@eecs.umich.edu wsm3 = *(uint64_t*)data; 1723881Ssaidi@eecs.umich.edu return No_Fault; 1733569Sgblack@eecs.umich.edu case TSDEV_PC_TBA0: 1743569Sgblack@eecs.umich.edu tba0 = *(uint64_t*)data; 1753881Ssaidi@eecs.umich.edu return No_Fault; 1763804Ssaidi@eecs.umich.edu case TSDEV_PC_TBA1: 1773881Ssaidi@eecs.umich.edu tba1 = *(uint64_t*)data; 1783826Ssaidi@eecs.umich.edu return No_Fault; 1793881Ssaidi@eecs.umich.edu case TSDEV_PC_TBA2: 1803881Ssaidi@eecs.umich.edu tba2 = *(uint64_t*)data; 1813881Ssaidi@eecs.umich.edu return No_Fault; 1823907Ssaidi@eecs.umich.edu case TSDEV_PC_TBA3: 1833907Ssaidi@eecs.umich.edu tba3 = *(uint64_t*)data; 1843929Ssaidi@eecs.umich.edu return No_Fault; 1853929Ssaidi@eecs.umich.edu case TSDEV_PC_PCTL: 1863907Ssaidi@eecs.umich.edu // might want to change the clock?? 1873907Ssaidi@eecs.umich.edu //*(uint64_t*)data; // try this 1883804Ssaidi@eecs.umich.edu return No_Fault; 1893804Ssaidi@eecs.umich.edu case TSDEV_PC_PLAT: 1903881Ssaidi@eecs.umich.edu panic("PC_PLAT not implemented\n"); 1913804Ssaidi@eecs.umich.edu case TSDEV_PC_RES: 1923804Ssaidi@eecs.umich.edu panic("PC_RES not implemented\n"); 1933804Ssaidi@eecs.umich.edu case TSDEV_PC_PERROR: 1943804Ssaidi@eecs.umich.edu panic("PC_PERROR not implemented\n"); 1953804Ssaidi@eecs.umich.edu case TSDEV_PC_PERRMASK: 1963804Ssaidi@eecs.umich.edu panic("PC_PERRMASK not implemented\n"); 1973804Ssaidi@eecs.umich.edu case TSDEV_PC_PERRSET: 1983569Sgblack@eecs.umich.edu panic("PC_PERRSET not implemented\n"); 1993863Ssaidi@eecs.umich.edu case TSDEV_PC_TLBIV: 2003863Ssaidi@eecs.umich.edu panic("PC_TLBIV not implemented\n"); 2013804Ssaidi@eecs.umich.edu case TSDEV_PC_TLBIA: 2025555Snate@binkert.org return No_Fault; // value ignored, supposted to invalidate SG TLB 2035555Snate@binkert.org case TSDEV_PC_PMONCTL: 2043804Ssaidi@eecs.umich.edu panic("PC_PMONCTL not implemented\n"); 2053804Ssaidi@eecs.umich.edu case TSDEV_PC_PMONCNT: 2063804Ssaidi@eecs.umich.edu panic("PC_PMONCTN not implemented\n"); 2073804Ssaidi@eecs.umich.edu default: 2083804Ssaidi@eecs.umich.edu panic("Default in PChip Read reached reading 0x%x\n", daddr); 2093569Sgblack@eecs.umich.edu 2103804Ssaidi@eecs.umich.edu } // uint64_t 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.edu break; 2135555Snate@binkert.org case sizeof(uint32_t): 2145555Snate@binkert.org case sizeof(uint16_t): 2153804Ssaidi@eecs.umich.edu case sizeof(uint8_t): 2163804Ssaidi@eecs.umich.edu default: 2173804Ssaidi@eecs.umich.edu panic("invalid access size(?) for tsunami register!\n\n"); 2183804Ssaidi@eecs.umich.edu } 2193804Ssaidi@eecs.umich.edu 2203811Ssaidi@eecs.umich.edu DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 2213811Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu return No_Fault; 2233804Ssaidi@eecs.umich.edu} 2245312Sgblack@eecs.umich.edu 2253804Ssaidi@eecs.umich.eduvoid 2263804Ssaidi@eecs.umich.eduTsunamiPChip::serialize(std::ostream &os) 2273804Ssaidi@eecs.umich.edu{ 2283804Ssaidi@eecs.umich.edu // code should be written 2293804Ssaidi@eecs.umich.edu} 2303804Ssaidi@eecs.umich.edu 2313804Ssaidi@eecs.umich.eduvoid 2323811Ssaidi@eecs.umich.eduTsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) 2333804Ssaidi@eecs.umich.edu{ 2343804Ssaidi@eecs.umich.edu //code should be written 2353804Ssaidi@eecs.umich.edu} 2363804Ssaidi@eecs.umich.edu 2373804Ssaidi@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 2383826Ssaidi@eecs.umich.edu 2393826Ssaidi@eecs.umich.edu SimObjectParam<Tsunami *> tsunami; 2404070Ssaidi@eecs.umich.edu SimObjectParam<MemoryController *> mmu; 2415555Snate@binkert.org Param<Addr> addr; 2425555Snate@binkert.org Param<Addr> mask; 2434070Ssaidi@eecs.umich.edu 2443804Ssaidi@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 2453804Ssaidi@eecs.umich.edu 2463804Ssaidi@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 2473804Ssaidi@eecs.umich.edu 2483804Ssaidi@eecs.umich.edu INIT_PARAM(tsunami, "Tsunami"), 2493804Ssaidi@eecs.umich.edu INIT_PARAM(mmu, "Memory Controller"), 2503804Ssaidi@eecs.umich.edu INIT_PARAM(addr, "Device Address"), 2513804Ssaidi@eecs.umich.edu INIT_PARAM(mask, "Address Mask") 2523804Ssaidi@eecs.umich.edu 2533804Ssaidi@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.eduCREATE_SIM_OBJECT(TsunamiPChip) 2563826Ssaidi@eecs.umich.edu{ 2573826Ssaidi@eecs.umich.edu return new TsunamiPChip(getInstanceName(), tsunami, addr, mask, mmu); 2583826Ssaidi@eecs.umich.edu} 2593863Ssaidi@eecs.umich.edu 2603826Ssaidi@eecs.umich.eduREGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) 2613826Ssaidi@eecs.umich.edu