tsunami_cchip.hh revision 817
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2003 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com */ 2812855Sgabeblack@google.com 2912855Sgabeblack@google.com/* @file 3012855Sgabeblack@google.com * Emulation of the Tsunami CChip CSRs 3112855Sgabeblack@google.com */ 3212855Sgabeblack@google.com 3312855Sgabeblack@google.com#ifndef __TSUNAMI_CCHIP_HH__ 3412855Sgabeblack@google.com#define __TSUNAMI_CCHIP_HH__ 3512855Sgabeblack@google.com 3612855Sgabeblack@google.com#include "mem/functional_mem/functional_memory.hh" 3712855Sgabeblack@google.com#include "dev/tsunami.hh" 3812855Sgabeblack@google.com 3912855Sgabeblack@google.com/* 4012855Sgabeblack@google.com * Tsunami CChip 4112855Sgabeblack@google.com */ 4212855Sgabeblack@google.comclass TsunamiCChip : public FunctionalMemory 4312855Sgabeblack@google.com{ 4412855Sgabeblack@google.com private: 4512855Sgabeblack@google.com Addr addr; 4612855Sgabeblack@google.com static const Addr size = 0xfff; 4712855Sgabeblack@google.com 4812855Sgabeblack@google.com protected: 4912855Sgabeblack@google.com /** 5012855Sgabeblack@google.com * pointer to the tsunami object. 5112855Sgabeblack@google.com * This is our access to all the other tsunami 5212855Sgabeblack@google.com * devices. 53 */ 54 Tsunami *tsunami; 55 56 /** 57 * The dims are device interrupt mask registers. 58 * One exists for each CPU, the DRIR X DIM = DIR 59 */ 60 uint64_t dim[Tsunami::Max_CPUs]; 61 62 /** 63 * The dirs are device interrupt registers. 64 * One exists for each CPU, the DRIR X DIM = DIR 65 */ 66 uint64_t dir[Tsunami::Max_CPUs]; 67 bool dirInterrupting[Tsunami::Max_CPUs]; 68 69 /** 70 * This register contains bits for each PCI interrupt 71 * that can occur. 72 */ 73 uint64_t drir; 74 75 public: 76 TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 77 MemoryController *mmu); 78 79 virtual Fault read(MemReqPtr &req, uint8_t *data); 80 virtual Fault write(MemReqPtr &req, const uint8_t *data); 81 82 void postDRIR(uint32_t interrupt); 83 void clearDRIR(uint32_t interrupt); 84 85 virtual void serialize(std::ostream &os); 86 virtual void unserialize(Checkpoint *cp, const std::string §ion); 87 88 uint64_t misc; 89 bool RTCInterrupting; 90}; 91 92#endif // __TSUNAMI_CCHIP_HH__ 93