tsunami_cchip.hh revision 1872 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Emulation of the Tsunami CChip CSRs
31 */
32
33#ifndef __TSUNAMI_CCHIP_HH__
34#define __TSUNAMI_CCHIP_HH__
35
36#include "dev/tsunami.hh"
37#include "base/range.hh"
38#include "dev/io_device.hh"
39
40class MemoryController;
41
42/**
43 * Tsunami CChip CSR Emulation. This device includes all the interrupt
44 * handling code for the chipset.
45 */
46class TsunamiCChip : public PioDevice
47{
48  private:
49    /** The base address of this device */
50    Addr addr;
51
52    /** The size of mappad from the above address */
53    static const Addr size = 0xfffffff;
54
55  protected:
56    /**
57     * pointer to the tsunami object.
58     * This is our access to all the other tsunami
59     * devices.
60     */
61    Tsunami *tsunami;
62
63    /**
64     * The dims are device interrupt mask registers.
65     * One exists for each CPU, the DRIR X DIM = DIR
66     */
67    uint64_t dim[Tsunami::Max_CPUs];
68
69    /**
70     * The dirs are device interrupt registers.
71     * One exists for each CPU, the DRIR X DIM = DIR
72     */
73    uint64_t dir[Tsunami::Max_CPUs];
74
75    /**
76     * This register contains bits for each PCI interrupt
77     * that can occur.
78     */
79    uint64_t drir;
80
81    /** Indicator of which CPUs have an IPI interrupt */
82    uint64_t ipint;
83
84    /** Indicator of which CPUs have an RTC interrupt */
85    uint64_t itint;
86
87  public:
88    /**
89     * Initialize the Tsunami CChip by setting all of the
90     * device register to 0.
91     * @param name name of this device.
92     * @param t pointer back to the Tsunami object that we belong to.
93     * @param a address we are mapped at.
94     * @param mmu pointer to the memory controller that sends us events.
95     * @param hier object to store parameters universal the device hierarchy
96     * @param bus The bus that this device is attached to
97     */
98    TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
99                 MemoryController *mmu, HierParams *hier, Bus *bus,
100                 Tick pio_latency);
101
102    /**
103      * Process a read to the CChip.
104      * @param req Contains the address to read from.
105      * @param data A pointer to write the read data to.
106      * @return The fault condition of the access.
107      */
108    virtual Fault read(MemReqPtr &req, uint8_t *data);
109
110
111    /**
112      * Process a write to the CChip.
113      * @param req Contains the address to write to.
114      * @param data The data to write.
115      * @return The fault condition of the access.
116      */
117    virtual Fault write(MemReqPtr &req, const uint8_t *data);
118
119    /**
120     * post an RTC interrupt to the CPU
121     */
122    void postRTC();
123
124    /**
125     * post an interrupt to the CPU.
126     * @param interrupt the interrupt number to post (0-64)
127     */
128    void postDRIR(uint32_t interrupt);
129
130    /**
131     * clear an interrupt previously posted to the CPU.
132     * @param interrupt the interrupt number to post (0-64)
133     */
134    void clearDRIR(uint32_t interrupt);
135
136    /**
137     * post an ipi interrupt  to the CPU.
138     * @param ipintr the cpu number to clear(bitvector)
139     */
140    void clearIPI(uint64_t ipintr);
141
142    /**
143     * clear a timer interrupt previously posted to the CPU.
144     * @param itintr the cpu number to clear(bitvector)
145     */
146    void clearITI(uint64_t itintr);
147
148    /**
149     * request an interrupt be posted to the CPU.
150     * @param ipreq the cpu number to interrupt(bitvector)
151     */
152    void reqIPI(uint64_t ipreq);
153
154
155    /**
156     * Serialize this object to the given output stream.
157     * @param os The stream to serialize to.
158     */
159    virtual void serialize(std::ostream &os);
160
161    /**
162     * Reconstruct the state of this object from a checkpoint.
163     * @param cp The checkpoint use.
164     * @param section The section name of this object
165     */
166    virtual void unserialize(Checkpoint *cp, const std::string &section);
167
168    /**
169     * Return how long this access will take.
170     * @param req the memory request to calcuate
171     * @return Tick when the request is done
172     */
173    Tick cacheAccess(MemReqPtr &req);
174};
175
176#endif // __TSUNAMI_CCHIP_HH__
177