backdoor.cc revision 926
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2001-2004 The Regents of The University of Michigan 38703Sandreas.hansson@arm.com * All rights reserved. 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68703Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78703Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88703Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98703Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108703Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118703Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128703Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138703Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157897Shestness@cs.utexas.edu * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A/* @file 302SN/A * System Console Definition 312SN/A */ 322SN/A 332SN/A#include <cstddef> 342SN/A#include <cstdio> 352SN/A#include <string> 362SN/A 372SN/A#include "base/inifile.hh" 382SN/A#include "base/str.hh" // for to_number() 392SN/A#include "base/trace.hh" 402665Ssaidi@eecs.umich.edu#include "cpu/base_cpu.hh" 412665Ssaidi@eecs.umich.edu#include "cpu/exec_context.hh" 422665Ssaidi@eecs.umich.edu#include "dev/alpha_console.hh" 432665Ssaidi@eecs.umich.edu#include "dev/console.hh" 447897Shestness@cs.utexas.edu#include "dev/simple_disk.hh" 452SN/A#include "dev/tlaser_clock.hh" 462SN/A#include "mem/bus/bus.hh" 472SN/A#include "mem/bus/pio_interface.hh" 482SN/A#include "mem/bus/pio_interface_impl.hh" 492SN/A#include "mem/functional_mem/memory_control.hh" 502SN/A#include "sim/builder.hh" 519645SAndreas.Sandberg@ARM.com#include "sim/system.hh" 5275SN/A#include "dev/tsunami_io.hh" 532SN/A#include "sim/sim_object.hh" 5410466Sandreas.hansson@arm.com#include "targetarch/byte_swap.hh" 552439SN/A 562439SN/Ausing namespace std; 57603SN/A 5810466Sandreas.hansson@arm.comAlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, 594762Snate@binkert.org System *system, BaseCPU *cpu, Platform *platform, 608703Sandreas.hansson@arm.com int num_cpus, MemoryController *mmu, Addr a, 612520SN/A HierParams *hier, Bus *bus) 629847Sandreas.hansson@arm.com : PioDevice(name), disk(d), console(cons), addr(a) 638931Sandreas.hansson@arm.com{ 644762Snate@binkert.org mmu->add_child(this, Range<Addr>(addr, addr + size)); 656658Snate@binkert.org 6610494Sandreas.hansson@arm.com if (bus) { 6710494Sandreas.hansson@arm.com pioInterface = newPioInterface(name, hier, bus, this, 6810494Sandreas.hansson@arm.com &AlphaConsole::cacheAccess); 6910494Sandreas.hansson@arm.com pioInterface->addAddrRange(addr, addr + size); 7010494Sandreas.hansson@arm.com } 7110494Sandreas.hansson@arm.com 7210494Sandreas.hansson@arm.com alphaAccess->last_offset = size - 1; 7310494Sandreas.hansson@arm.com alphaAccess->kernStart = system->getKernelStart(); 741634SN/A alphaAccess->kernEnd = system->getKernelEnd(); 758769Sgblack@eecs.umich.edu alphaAccess->entryPoint = system->getKernelEntry(); 768769Sgblack@eecs.umich.edu 771634SN/A alphaAccess->version = ALPHA_ACCESS_VERSION; 78803SN/A alphaAccess->numCPUs = num_cpus; 798769Sgblack@eecs.umich.edu alphaAccess->mem_size = system->physmem->size(); 802SN/A alphaAccess->cpuClock = cpu->getFreq() / 1000000; 818703Sandreas.hansson@arm.com alphaAccess->intrClockFrequency = platform->intrFrequency(); 822SN/A alphaAccess->diskUnit = 1; 838703Sandreas.hansson@arm.com 848703Sandreas.hansson@arm.com alphaAccess->diskCount = 0; 858703Sandreas.hansson@arm.com alphaAccess->diskPAddr = 0; 868703Sandreas.hansson@arm.com alphaAccess->diskBlock = 0; 878703Sandreas.hansson@arm.com alphaAccess->diskOperation = 0; 888703Sandreas.hansson@arm.com alphaAccess->outputChar = 0; 898703Sandreas.hansson@arm.com alphaAccess->inputChar = 0; 908922Swilliam.wang@arm.com alphaAccess->bootStrapImpure = 0; 918703Sandreas.hansson@arm.com alphaAccess->bootStrapCPU = 0; 928703Sandreas.hansson@arm.com alphaAccess->align2 = 0; 938703Sandreas.hansson@arm.com} 948703Sandreas.hansson@arm.com 958703Sandreas.hansson@arm.comFault 968703Sandreas.hansson@arm.comAlphaConsole::read(MemReqPtr &req, uint8_t *data) 978703Sandreas.hansson@arm.com{ 988922Swilliam.wang@arm.com memset(data, 0, req->size); 998703Sandreas.hansson@arm.com 1008975Sandreas.hansson@arm.com Addr daddr = req->paddr - (addr & PA_IMPL_MASK); 1018703Sandreas.hansson@arm.com 1028922Swilliam.wang@arm.com switch (req->size) 1038922Swilliam.wang@arm.com { 1048703Sandreas.hansson@arm.com case sizeof(uint32_t): 1058703Sandreas.hansson@arm.com DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint32_t*)data); 1068703Sandreas.hansson@arm.com switch (daddr) 1078703Sandreas.hansson@arm.com { 108603SN/A case offsetof(AlphaAccess, last_offset): 1092901Ssaidi@eecs.umich.edu *(uint32_t*)data = alphaAccess->last_offset; 1108703Sandreas.hansson@arm.com break; 1118706Sandreas.hansson@arm.com case offsetof(AlphaAccess, version): 1128706Sandreas.hansson@arm.com *(uint32_t*)data = alphaAccess->version; 1138706Sandreas.hansson@arm.com break; 1148706Sandreas.hansson@arm.com case offsetof(AlphaAccess, numCPUs): 1158706Sandreas.hansson@arm.com *(uint32_t*)data = alphaAccess->numCPUs; 1168706Sandreas.hansson@arm.com break; 1178852Sandreas.hansson@arm.com case offsetof(AlphaAccess, bootStrapCPU): 1188703Sandreas.hansson@arm.com *(uint32_t*)data = alphaAccess->bootStrapCPU; 1198703Sandreas.hansson@arm.com break; 1208703Sandreas.hansson@arm.com case offsetof(AlphaAccess, intrClockFrequency): 1218703Sandreas.hansson@arm.com *(uint32_t*)data = alphaAccess->intrClockFrequency; 1228852Sandreas.hansson@arm.com break; 1238703Sandreas.hansson@arm.com default: 1248922Swilliam.wang@arm.com panic("Unknown 32bit access, %#x\n", daddr); 1258703Sandreas.hansson@arm.com } 1268703Sandreas.hansson@arm.com break; 1278703Sandreas.hansson@arm.com case sizeof(uint64_t): 1288703Sandreas.hansson@arm.com DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint64_t*)data); 1299294Sandreas.hansson@arm.com switch (daddr) 1309294Sandreas.hansson@arm.com { 1318703Sandreas.hansson@arm.com case offsetof(AlphaAccess, inputChar): 1329524SAndreas.Sandberg@ARM.com *(uint64_t*)data = console->console_in(); 1339524SAndreas.Sandberg@ARM.com break; 1349524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, cpuClock): 1359524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->cpuClock; 1369524SAndreas.Sandberg@ARM.com break; 1379524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, mem_size): 1389524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->mem_size; 1399524SAndreas.Sandberg@ARM.com break; 1409524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, kernStart): 1419524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->kernStart; 1429524SAndreas.Sandberg@ARM.com break; 1439524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, kernEnd): 1449524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->kernEnd; 1454762Snate@binkert.org break; 1462901Ssaidi@eecs.umich.edu case offsetof(AlphaAccess, entryPoint): 1479524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->entryPoint; 1489524SAndreas.Sandberg@ARM.com break; 1499524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, diskUnit): 1509524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->diskUnit; 1519524SAndreas.Sandberg@ARM.com break; 1529524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, diskCount): 1539524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->diskCount; 1549524SAndreas.Sandberg@ARM.com break; 1559524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, diskPAddr): 1569524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->diskPAddr; 1579524SAndreas.Sandberg@ARM.com break; 1589524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, diskBlock): 1599524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->diskBlock; 1609524SAndreas.Sandberg@ARM.com break; 1619524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, diskOperation): 1629524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->diskOperation; 1639524SAndreas.Sandberg@ARM.com break; 1649524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, outputChar): 1659524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->outputChar; 1669524SAndreas.Sandberg@ARM.com break; 1679524SAndreas.Sandberg@ARM.com case offsetof(AlphaAccess, bootStrapImpure): 1689524SAndreas.Sandberg@ARM.com *(uint64_t*)data = alphaAccess->bootStrapImpure; 1699524SAndreas.Sandberg@ARM.com break; 1709524SAndreas.Sandberg@ARM.com default: 1719524SAndreas.Sandberg@ARM.com panic("Unknown 64bit access, %#x\n", daddr); 1729524SAndreas.Sandberg@ARM.com } 1739524SAndreas.Sandberg@ARM.com break; 1749524SAndreas.Sandberg@ARM.com default: 1759524SAndreas.Sandberg@ARM.com return Machine_Check_Fault; 1769524SAndreas.Sandberg@ARM.com } 1779524SAndreas.Sandberg@ARM.com 1789524SAndreas.Sandberg@ARM.com return No_Fault; 1799524SAndreas.Sandberg@ARM.com} 1809524SAndreas.Sandberg@ARM.com 1819524SAndreas.Sandberg@ARM.comFault 1829524SAndreas.Sandberg@ARM.comAlphaConsole::write(MemReqPtr &req, const uint8_t *data) 1839524SAndreas.Sandberg@ARM.com{ 1842901Ssaidi@eecs.umich.edu uint64_t val; 1854762Snate@binkert.org 1869524SAndreas.Sandberg@ARM.com switch (req->size) { 1872901Ssaidi@eecs.umich.edu case sizeof(uint32_t): 1889814Sandreas.hansson@arm.com val = *(uint32_t *)data; 1899814Sandreas.hansson@arm.com break; 1909814Sandreas.hansson@arm.com 1919814Sandreas.hansson@arm.com case sizeof(uint64_t): 1929814Sandreas.hansson@arm.com val = *(uint64_t *)data; 1939850Sandreas.hansson@arm.com break; 1942SN/A default: 1959850Sandreas.hansson@arm.com return Machine_Check_Fault; 1962SN/A } 1972680Sktlim@umich.edu 1985714Shsul@eecs.umich.edu Addr daddr = req->paddr - (addr & PA_IMPL_MASK); 1991806SN/A ExecContext *other_xc; 2006221Snate@binkert.org 2015713Shsul@eecs.umich.edu switch (daddr) { 2025713Shsul@eecs.umich.edu case offsetof(AlphaAccess, diskUnit): 2035713Shsul@eecs.umich.edu alphaAccess->diskUnit = val; 2045713Shsul@eecs.umich.edu break; 2055714Shsul@eecs.umich.edu 2061806SN/A case offsetof(AlphaAccess, diskCount): 2076227Snate@binkert.org alphaAccess->diskCount = val; 2085714Shsul@eecs.umich.edu break; 2091806SN/A 210180SN/A case offsetof(AlphaAccess, diskPAddr): 2116029Ssteve.reinhardt@amd.com alphaAccess->diskPAddr = val; 2126029Ssteve.reinhardt@amd.com break; 2136029Ssteve.reinhardt@amd.com 2146029Ssteve.reinhardt@amd.com case offsetof(AlphaAccess, diskBlock): 2158765Sgblack@eecs.umich.edu alphaAccess->diskBlock = val; 2168765Sgblack@eecs.umich.edu break; 2172378SN/A 2182378SN/A case offsetof(AlphaAccess, diskOperation): 2192520SN/A if (val == 0x13) 2202520SN/A disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 2218852Sandreas.hansson@arm.com alphaAccess->diskCount); 2222520SN/A else 2231885SN/A panic("Invalid disk operation!"); 2241070SN/A 225954SN/A break; 2261070SN/A 2271070SN/A case offsetof(AlphaAccess, outputChar): 2281070SN/A console->out((char)(val & 0xff), false); 2291070SN/A break; 2301070SN/A 2311070SN/A case offsetof(AlphaAccess, bootStrapImpure): 2321070SN/A alphaAccess->bootStrapImpure = val; 2331070SN/A break; 2341070SN/A 2351070SN/A case offsetof(AlphaAccess, bootStrapCPU): 2361070SN/A warn("%d: Trying to launch another CPU!", curTick); 2371070SN/A assert(val > 0 && "Must not access primary cpu"); 2387580SAli.Saidi@arm.com 2397580SAli.Saidi@arm.com other_xc = req->xc->system->execContexts[val]; 2407580SAli.Saidi@arm.com other_xc->regs.intRegFile[16] = val; 2417580SAli.Saidi@arm.com other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val; 2427580SAli.Saidi@arm.com other_xc->regs.intRegFile[0] = val; 2437580SAli.Saidi@arm.com other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; 2447580SAli.Saidi@arm.com other_xc->activate(); //Start the cpu 2457580SAli.Saidi@arm.com break; 24610037SARM gem5 Developers 24710037SARM gem5 Developers default: 24810037SARM gem5 Developers return Machine_Check_Fault; 24910037SARM gem5 Developers } 25010037SARM gem5 Developers 25110037SARM gem5 Developers return No_Fault; 25210037SARM gem5 Developers} 2534997Sgblack@eecs.umich.edu 2547770SAli.Saidi@ARM.comTick 2554997Sgblack@eecs.umich.eduAlphaConsole::cacheAccess(MemReqPtr &req) 2564997Sgblack@eecs.umich.edu{ 2574997Sgblack@eecs.umich.edu return curTick + 1000; 2584997Sgblack@eecs.umich.edu} 2597770SAli.Saidi@ARM.com 2604997Sgblack@eecs.umich.eduvoid 2614997Sgblack@eecs.umich.eduAlphaAccess::serialize(ostream &os) 2628931Sandreas.hansson@arm.com{ 2638931Sandreas.hansson@arm.com SERIALIZE_SCALAR(last_offset); 2648931Sandreas.hansson@arm.com SERIALIZE_SCALAR(version); 2655795Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(numCPUs); 2668931Sandreas.hansson@arm.com SERIALIZE_SCALAR(mem_size); 2675795Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(cpuClock); 2685795Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(intrClockFrequency); 2698931Sandreas.hansson@arm.com SERIALIZE_SCALAR(kernStart); 2708931Sandreas.hansson@arm.com SERIALIZE_SCALAR(kernEnd); 2718931Sandreas.hansson@arm.com SERIALIZE_SCALAR(entryPoint); 2728931Sandreas.hansson@arm.com SERIALIZE_SCALAR(diskUnit); 2738931Sandreas.hansson@arm.com SERIALIZE_SCALAR(diskCount); 2748931Sandreas.hansson@arm.com SERIALIZE_SCALAR(diskPAddr); 2758931Sandreas.hansson@arm.com SERIALIZE_SCALAR(diskBlock); 2768931Sandreas.hansson@arm.com SERIALIZE_SCALAR(diskOperation); 2778931Sandreas.hansson@arm.com SERIALIZE_SCALAR(outputChar); 2788931Sandreas.hansson@arm.com SERIALIZE_SCALAR(inputChar); 2795795Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(bootStrapImpure); 28010467Sandreas.hansson@arm.com SERIALIZE_SCALAR(bootStrapCPU); 28110467Sandreas.hansson@arm.com} 28210467Sandreas.hansson@arm.com 28310467Sandreas.hansson@arm.comvoid 28410467Sandreas.hansson@arm.comAlphaAccess::unserialize(Checkpoint *cp, const std::string §ion) 28510466Sandreas.hansson@arm.com{ 28610466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(last_offset); 28710466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(version); 28810466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(numCPUs); 28910466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(mem_size); 29010466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(cpuClock); 29110466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(intrClockFrequency); 29210466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(kernStart); 29310466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(kernEnd); 29410466Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(entryPoint); 2951885SN/A UNSERIALIZE_SCALAR(diskUnit); 2968931Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(diskCount); 2978931Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(diskPAddr); 2988931Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(diskBlock); 2994762Snate@binkert.org UNSERIALIZE_SCALAR(diskOperation); 3009814Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(outputChar); 3019814Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(inputChar); 3029814Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bootStrapImpure); 3037914SBrad.Beckmann@amd.com UNSERIALIZE_SCALAR(bootStrapCPU); 3047914SBrad.Beckmann@amd.com} 3058666SPrakash.Ramrakhyani@arm.com 3067914SBrad.Beckmann@amd.comvoid 3077914SBrad.Beckmann@amd.comAlphaConsole::serialize(ostream &os) 3088832SAli.Saidi@ARM.com{ 3098832SAli.Saidi@ARM.com alphaAccess->serialize(os); 3108832SAli.Saidi@ARM.com} 3118832SAli.Saidi@ARM.com 3128832SAli.Saidi@ARM.comvoid 3138832SAli.Saidi@ARM.comAlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) 3148832SAli.Saidi@ARM.com{ 3157914SBrad.Beckmann@amd.com alphaAccess->unserialize(cp, section); 3168832SAli.Saidi@ARM.com} 3178832SAli.Saidi@ARM.com 3188832SAli.Saidi@ARM.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 3198832SAli.Saidi@ARM.com 3208832SAli.Saidi@ARM.com SimObjectParam<SimConsole *> sim_console; 3218832SAli.Saidi@ARM.com SimObjectParam<SimpleDisk *> disk; 3228832SAli.Saidi@ARM.com Param<int> num_cpus; 3238832SAli.Saidi@ARM.com SimObjectParam<MemoryController *> mmu; 3248832SAli.Saidi@ARM.com Param<Addr> addr; 3258832SAli.Saidi@ARM.com SimObjectParam<System *> system; 3268832SAli.Saidi@ARM.com SimObjectParam<BaseCPU *> cpu; 3278832SAli.Saidi@ARM.com SimObjectParam<Platform *> platform; 3288832SAli.Saidi@ARM.com SimObjectParam<Bus*> io_bus; 3298832SAli.Saidi@ARM.com SimObjectParam<HierParams *> hier; 3308832SAli.Saidi@ARM.com 3318832SAli.Saidi@ARM.comEND_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 3328832SAli.Saidi@ARM.com 3338832SAli.Saidi@ARM.comBEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 3348832SAli.Saidi@ARM.com 3358832SAli.Saidi@ARM.com INIT_PARAM(sim_console, "The Simulator Console"), 3368832SAli.Saidi@ARM.com INIT_PARAM(disk, "Simple Disk"), 3378666SPrakash.Ramrakhyani@arm.com INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1), 3387914SBrad.Beckmann@amd.com INIT_PARAM(mmu, "Memory Controller"), 3397914SBrad.Beckmann@amd.com INIT_PARAM(addr, "Device Address"), 3407914SBrad.Beckmann@amd.com INIT_PARAM(system, "system object"), 3417914SBrad.Beckmann@amd.com INIT_PARAM(cpu, "Processor"), 3428666SPrakash.Ramrakhyani@arm.com INIT_PARAM(platform, "platform"), 3437914SBrad.Beckmann@amd.com INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), 3447914SBrad.Beckmann@amd.com INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 3457914SBrad.Beckmann@amd.com 3467914SBrad.Beckmann@amd.comEND_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 3477914SBrad.Beckmann@amd.com 3487914SBrad.Beckmann@amd.comCREATE_SIM_OBJECT(AlphaConsole) 3497914SBrad.Beckmann@amd.com{ 3507914SBrad.Beckmann@amd.com return new AlphaConsole(getInstanceName(), sim_console, disk, 3517914SBrad.Beckmann@amd.com system, cpu, platform, num_cpus, mmu, 35210037SARM gem5 Developers addr, hier, io_bus); 3537914SBrad.Beckmann@amd.com} 3547914SBrad.Beckmann@amd.com 3557914SBrad.Beckmann@amd.comREGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 3567914SBrad.Beckmann@amd.com