backdoor.cc revision 8806
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Nathan Binkert
292665SN/A *          Ali Saidi
302665SN/A *          Steve Reinhardt
312665SN/A *          Erik Hallnor
322SN/A */
332SN/A
341722SN/A/** @file
355480Snate@binkert.org * Alpha Console Backdoor Definition
362SN/A */
372SN/A
38146SN/A#include <cstddef>
392SN/A#include <string>
402SN/A
412158SN/A#include "arch/alpha/system.hh"
42146SN/A#include "base/inifile.hh"
431805SN/A#include "base/str.hh"
44146SN/A#include "base/trace.hh"
451717SN/A#include "cpu/base.hh"
462680SN/A#include "cpu/thread_context.hh"
478232Snate@binkert.org#include "debug/AlphaBackdoor.hh"
485480Snate@binkert.org#include "dev/alpha/backdoor.hh"
498741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh"
508741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh"
518741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh"
522521SN/A#include "dev/platform.hh"
5356SN/A#include "dev/simple_disk.hh"
545478SN/A#include "dev/terminal.hh"
553348SN/A#include "mem/packet.hh"
563348SN/A#include "mem/packet_access.hh"
572521SN/A#include "mem/physical.hh"
585480Snate@binkert.org#include "params/AlphaBackdoor.hh"
591805SN/A#include "sim/sim_object.hh"
602SN/A
612SN/Ausing namespace std;
622107SN/Ausing namespace AlphaISA;
632SN/A
645480Snate@binkert.orgAlphaBackdoor::AlphaBackdoor(const Params *p)
655478SN/A    : BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
668806Sgblack@eecs.umich.edu      system(p->system), cpu(p->cpu)
672SN/A{
68545SN/A
692521SN/A    pioSize = sizeof(struct AlphaAccess);
702521SN/A
712521SN/A    alphaAccess = new Access();
722521SN/A    alphaAccess->last_offset = pioSize - 1;
732SN/A
742SN/A    alphaAccess->version = ALPHA_ACCESS_VERSION;
752SN/A    alphaAccess->diskUnit = 1;
76926SN/A
77926SN/A    alphaAccess->diskCount = 0;
78926SN/A    alphaAccess->diskPAddr = 0;
79926SN/A    alphaAccess->diskBlock = 0;
80926SN/A    alphaAccess->diskOperation = 0;
81926SN/A    alphaAccess->outputChar = 0;
82926SN/A    alphaAccess->inputChar = 0;
834395SN/A    std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
841805SN/A
852SN/A}
862SN/A
871634SN/Avoid
885480Snate@binkert.orgAlphaBackdoor::startup()
891634SN/A{
902549SN/A    system->setAlphaAccess(pioAddr);
915714Shsul@eecs.umich.edu    alphaAccess->numCPUs = system->numContexts();
921634SN/A    alphaAccess->kernStart = system->getKernelStart();
931634SN/A    alphaAccess->kernEnd = system->getKernelEnd();
941634SN/A    alphaAccess->entryPoint = system->getKernelEntry();
951634SN/A    alphaAccess->mem_size = system->physmem->size();
961634SN/A    alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
978741Sgblack@eecs.umich.edu    Tsunami *tsunami = dynamic_cast<Tsunami *>(params()->platform);
988806Sgblack@eecs.umich.edu    if (!tsunami)
998806Sgblack@eecs.umich.edu        fatal("Platform is not Tsunami.\n");
1008741Sgblack@eecs.umich.edu    alphaAccess->intrClockFrequency = tsunami->io->frequency();
1011634SN/A}
1021634SN/A
1032512SN/ATick
1045480Snate@binkert.orgAlphaBackdoor::read(PacketPtr pkt)
1052SN/A{
1062SN/A
1072512SN/A    /** XXX Do we want to push the addr munging to a bus brige or something? So
1082512SN/A     * the device has it's physical address and then the bridge adds on whatever
1092512SN/A     * machine dependent address swizzle is required?
1102512SN/A     */
111540SN/A
1122641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
1132522SN/A
1142641SN/A    Addr daddr = pkt->getAddr() - pioAddr;
1152512SN/A
1162630SN/A    pkt->allocate();
1174986SN/A    pkt->makeAtomicResponse();
1182521SN/A
1192641SN/A    switch (pkt->getSize())
120873SN/A    {
121873SN/A        case sizeof(uint32_t):
122873SN/A            switch (daddr)
123873SN/A            {
124873SN/A                case offsetof(AlphaAccess, last_offset):
1252630SN/A                    pkt->set(alphaAccess->last_offset);
126873SN/A                    break;
127873SN/A                case offsetof(AlphaAccess, version):
1282630SN/A                    pkt->set(alphaAccess->version);
129873SN/A                    break;
130873SN/A                case offsetof(AlphaAccess, numCPUs):
1312630SN/A                    pkt->set(alphaAccess->numCPUs);
132873SN/A                    break;
133873SN/A                case offsetof(AlphaAccess, intrClockFrequency):
1342630SN/A                    pkt->set(alphaAccess->intrClockFrequency);
135873SN/A                    break;
136873SN/A                default:
1372512SN/A                    /* Old console code read in everyting as a 32bit int
1382512SN/A                     * we now break that for better error checking.
1392512SN/A                     */
1404870SN/A                  pkt->setBadAddress();
141873SN/A            }
1425480Snate@binkert.org            DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
1432630SN/A                    pkt->get<uint32_t>());
144873SN/A            break;
145873SN/A        case sizeof(uint64_t):
146873SN/A            switch (daddr)
147873SN/A            {
148873SN/A                case offsetof(AlphaAccess, inputChar):
1495478SN/A                    pkt->set(terminal->console_in());
150873SN/A                    break;
151873SN/A                case offsetof(AlphaAccess, cpuClock):
1522630SN/A                    pkt->set(alphaAccess->cpuClock);
153873SN/A                    break;
154873SN/A                case offsetof(AlphaAccess, mem_size):
1552630SN/A                    pkt->set(alphaAccess->mem_size);
156873SN/A                    break;
157873SN/A                case offsetof(AlphaAccess, kernStart):
1582630SN/A                    pkt->set(alphaAccess->kernStart);
159873SN/A                    break;
160873SN/A                case offsetof(AlphaAccess, kernEnd):
1612630SN/A                    pkt->set(alphaAccess->kernEnd);
162873SN/A                    break;
163873SN/A                case offsetof(AlphaAccess, entryPoint):
1642630SN/A                    pkt->set(alphaAccess->entryPoint);
165873SN/A                    break;
166873SN/A                case offsetof(AlphaAccess, diskUnit):
1672630SN/A                    pkt->set(alphaAccess->diskUnit);
168873SN/A                    break;
169873SN/A                case offsetof(AlphaAccess, diskCount):
1702630SN/A                    pkt->set(alphaAccess->diskCount);
171873SN/A                    break;
172873SN/A                case offsetof(AlphaAccess, diskPAddr):
1732630SN/A                    pkt->set(alphaAccess->diskPAddr);
174873SN/A                    break;
175873SN/A                case offsetof(AlphaAccess, diskBlock):
1762630SN/A                    pkt->set(alphaAccess->diskBlock);
177873SN/A                    break;
178873SN/A                case offsetof(AlphaAccess, diskOperation):
1792630SN/A                    pkt->set(alphaAccess->diskOperation);
180873SN/A                    break;
181873SN/A                case offsetof(AlphaAccess, outputChar):
1822630SN/A                    pkt->set(alphaAccess->outputChar);
183873SN/A                    break;
184873SN/A                default:
1852114SN/A                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
1862114SN/A                                 sizeof(alphaAccess->cpuStack[0]);
1872114SN/A
1882114SN/A                    if (cpunum >= 0 && cpunum < 64)
1892630SN/A                        pkt->set(alphaAccess->cpuStack[cpunum]);
1902114SN/A                    else
1912114SN/A                        panic("Unknown 64bit access, %#x\n", daddr);
192873SN/A            }
1935480Snate@binkert.org            DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
1942630SN/A                    pkt->get<uint64_t>());
195873SN/A            break;
196873SN/A        default:
1974870SN/A          pkt->setBadAddress();
1982SN/A    }
1992512SN/A    return pioDelay;
2002SN/A}
2012SN/A
2022512SN/ATick
2035480Snate@binkert.orgAlphaBackdoor::write(PacketPtr pkt)
2042SN/A{
2052641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
2062641SN/A    Addr daddr = pkt->getAddr() - pioAddr;
207430SN/A
2082630SN/A    uint64_t val = pkt->get<uint64_t>();
2092641SN/A    assert(pkt->getSize() == sizeof(uint64_t));
2102SN/A
211430SN/A    switch (daddr) {
212430SN/A      case offsetof(AlphaAccess, diskUnit):
2132SN/A        alphaAccess->diskUnit = val;
214430SN/A        break;
2152SN/A
216430SN/A      case offsetof(AlphaAccess, diskCount):
2172SN/A        alphaAccess->diskCount = val;
218430SN/A        break;
2192SN/A
220430SN/A      case offsetof(AlphaAccess, diskPAddr):
2212SN/A        alphaAccess->diskPAddr = val;
222430SN/A        break;
2232SN/A
224430SN/A      case offsetof(AlphaAccess, diskBlock):
2252SN/A        alphaAccess->diskBlock = val;
226430SN/A        break;
2272SN/A
228430SN/A      case offsetof(AlphaAccess, diskOperation):
2292SN/A        if (val == 0x13)
2302SN/A            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
2312SN/A                       alphaAccess->diskCount);
2322SN/A        else
2332SN/A            panic("Invalid disk operation!");
2342SN/A
235430SN/A        break;
2362SN/A
237430SN/A      case offsetof(AlphaAccess, outputChar):
2385478SN/A        terminal->out((char)(val & 0xff));
239430SN/A        break;
2402SN/A
241430SN/A      default:
2422114SN/A        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
2432114SN/A                     sizeof(alphaAccess->cpuStack[0]);
2447823Ssteve.reinhardt@amd.com        inform("Launching CPU %d @ %d", cpunum, curTick());
2452114SN/A        assert(val > 0 && "Must not access primary cpu");
2462114SN/A        if (cpunum >= 0 && cpunum < 64)
2472114SN/A            alphaAccess->cpuStack[cpunum] = val;
2482114SN/A        else
2492114SN/A            panic("Unknown 64bit access, %#x\n", daddr);
2502SN/A    }
2512SN/A
2524870SN/A    pkt->makeAtomicResponse();
2532SN/A
2542512SN/A    return pioDelay;
255545SN/A}
256545SN/A
2572SN/Avoid
2585480Snate@binkert.orgAlphaBackdoor::Access::serialize(ostream &os)
2592SN/A{
260222SN/A    SERIALIZE_SCALAR(last_offset);
261222SN/A    SERIALIZE_SCALAR(version);
262222SN/A    SERIALIZE_SCALAR(numCPUs);
263222SN/A    SERIALIZE_SCALAR(mem_size);
264222SN/A    SERIALIZE_SCALAR(cpuClock);
265222SN/A    SERIALIZE_SCALAR(intrClockFrequency);
266222SN/A    SERIALIZE_SCALAR(kernStart);
267222SN/A    SERIALIZE_SCALAR(kernEnd);
268222SN/A    SERIALIZE_SCALAR(entryPoint);
269222SN/A    SERIALIZE_SCALAR(diskUnit);
270222SN/A    SERIALIZE_SCALAR(diskCount);
271222SN/A    SERIALIZE_SCALAR(diskPAddr);
272222SN/A    SERIALIZE_SCALAR(diskBlock);
273222SN/A    SERIALIZE_SCALAR(diskOperation);
274222SN/A    SERIALIZE_SCALAR(outputChar);
275430SN/A    SERIALIZE_SCALAR(inputChar);
2762114SN/A    SERIALIZE_ARRAY(cpuStack,64);
2772SN/A}
2782SN/A
2792SN/Avoid
2805480Snate@binkert.orgAlphaBackdoor::Access::unserialize(Checkpoint *cp, const std::string &section)
2812SN/A{
282222SN/A    UNSERIALIZE_SCALAR(last_offset);
283222SN/A    UNSERIALIZE_SCALAR(version);
284222SN/A    UNSERIALIZE_SCALAR(numCPUs);
285222SN/A    UNSERIALIZE_SCALAR(mem_size);
286222SN/A    UNSERIALIZE_SCALAR(cpuClock);
287222SN/A    UNSERIALIZE_SCALAR(intrClockFrequency);
288222SN/A    UNSERIALIZE_SCALAR(kernStart);
289222SN/A    UNSERIALIZE_SCALAR(kernEnd);
290222SN/A    UNSERIALIZE_SCALAR(entryPoint);
291222SN/A    UNSERIALIZE_SCALAR(diskUnit);
292222SN/A    UNSERIALIZE_SCALAR(diskCount);
293222SN/A    UNSERIALIZE_SCALAR(diskPAddr);
294222SN/A    UNSERIALIZE_SCALAR(diskBlock);
295222SN/A    UNSERIALIZE_SCALAR(diskOperation);
296222SN/A    UNSERIALIZE_SCALAR(outputChar);
297430SN/A    UNSERIALIZE_SCALAR(inputChar);
2982114SN/A    UNSERIALIZE_ARRAY(cpuStack, 64);
299217SN/A}
3002SN/A
301217SN/Avoid
3025480Snate@binkert.orgAlphaBackdoor::serialize(ostream &os)
303217SN/A{
304217SN/A    alphaAccess->serialize(os);
305217SN/A}
306217SN/A
307217SN/Avoid
3085480Snate@binkert.orgAlphaBackdoor::unserialize(Checkpoint *cp, const std::string &section)
309217SN/A{
310237SN/A    alphaAccess->unserialize(cp, section);
3112SN/A}
3122SN/A
3135480Snate@binkert.orgAlphaBackdoor *
3145480Snate@binkert.orgAlphaBackdoorParams::create()
3152SN/A{
3165480Snate@binkert.org    return new AlphaBackdoor(this);
3172SN/A}
318