backdoor.cc revision 540 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* @file
30 * System Console Definition
31 */
32
33#include <cstddef>
34#include <cstdio>
35#include <string>
36
37#include "base/inifile.hh"
38#include "base/str.hh"	// for to_number()
39#include "base/trace.hh"
40#include "cpu/base_cpu.hh"
41#include "cpu/exec_context.hh"
42#include "dev/alpha_console.hh"
43#include "dev/console.hh"
44#include "dev/simple_disk.hh"
45#include "dev/tlaser_clock.hh"
46#include "mem/functional_mem/memory_control.hh"
47#include "sim/builder.hh"
48#include "sim/system.hh"
49
50using namespace std;
51
52AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
53                           System *system, BaseCPU *cpu, TlaserClock *clock,
54                           int num_cpus, MemoryController *mmu, Addr a)
55    : FunctionalMemory(name), disk(d), console(cons), addr(a)
56{
57    mmu->add_child(this, Range<Addr>(addr, addr + size));
58
59    consoleData = new uint8_t[size];
60    memset(consoleData, 0, size);
61
62    alphaAccess->last_offset = size - 1;
63    alphaAccess->kernStart = system->getKernelStart();
64    alphaAccess->kernEnd = system->getKernelEnd();
65    alphaAccess->entryPoint = system->getKernelEntry();
66
67    alphaAccess->version = ALPHA_ACCESS_VERSION;
68    alphaAccess->numCPUs = num_cpus;
69    alphaAccess->mem_size = system->physmem->size();
70    alphaAccess->cpuClock = cpu->getFreq() / 1000000;
71    alphaAccess->intrClockFrequency = clock->frequency();
72
73    alphaAccess->diskUnit = 1;
74}
75
76Fault
77AlphaConsole::read(MemReqPtr &req, uint8_t *data)
78{
79    memset(data, 0, req->size);
80    uint64_t val;
81
82    Addr daddr = req->paddr - addr;
83
84    switch (daddr) {
85      case offsetof(AlphaAccess, inputChar):
86        val = console->console_in();
87        break;
88
89      default:
90        val = *(uint64_t *)(consoleData + daddr);
91        break;
92    }
93
94    DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, val);
95
96    switch (req->size) {
97      case sizeof(uint32_t):
98        *(uint32_t *)data = (uint32_t)val;
99        break;
100
101      case sizeof(uint64_t):
102        *(uint64_t *)data = val;
103        break;
104
105      default:
106        return Machine_Check_Fault;
107    }
108
109
110    return No_Fault;
111}
112
113Fault
114AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
115{
116    uint64_t val;
117
118    switch (req->size) {
119      case sizeof(uint32_t):
120        val = *(uint32_t *)data;
121        break;
122
123      case sizeof(uint64_t):
124        val = *(uint64_t *)data;
125        break;
126      default:
127        return Machine_Check_Fault;
128    }
129
130    Addr daddr = req->paddr - addr;
131    ExecContext *other_xc;
132
133    switch (daddr) {
134      case offsetof(AlphaAccess, diskUnit):
135        alphaAccess->diskUnit = val;
136        break;
137
138      case offsetof(AlphaAccess, diskCount):
139        alphaAccess->diskCount = val;
140        break;
141
142      case offsetof(AlphaAccess, diskPAddr):
143        alphaAccess->diskPAddr = val;
144        break;
145
146      case offsetof(AlphaAccess, diskBlock):
147        alphaAccess->diskBlock = val;
148        break;
149
150      case offsetof(AlphaAccess, diskOperation):
151        if (val == 0x13)
152            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
153                       alphaAccess->diskCount);
154        else
155            panic("Invalid disk operation!");
156
157        break;
158
159      case offsetof(AlphaAccess, outputChar):
160        console->out((char)(val & 0xff), false);
161        break;
162
163      case offsetof(AlphaAccess, bootStrapImpure):
164        alphaAccess->bootStrapImpure = val;
165        break;
166
167      case offsetof(AlphaAccess, bootStrapCPU):
168        warn("%d: Trying to launch another CPU!", curTick);
169        assert(val > 0 && "Must not access primary cpu");
170
171        other_xc = req->xc->system->execContexts[val];
172        other_xc->regs.intRegFile[16] = val;
173        other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
174        other_xc->regs.intRegFile[0] = val;
175        other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
176        other_xc->activate(); //Start the cpu
177        break;
178
179      default:
180        return Machine_Check_Fault;
181    }
182
183    return No_Fault;
184}
185
186void
187AlphaAccess::serialize(ostream &os)
188{
189    SERIALIZE_SCALAR(last_offset);
190    SERIALIZE_SCALAR(version);
191    SERIALIZE_SCALAR(numCPUs);
192    SERIALIZE_SCALAR(mem_size);
193    SERIALIZE_SCALAR(cpuClock);
194    SERIALIZE_SCALAR(intrClockFrequency);
195    SERIALIZE_SCALAR(kernStart);
196    SERIALIZE_SCALAR(kernEnd);
197    SERIALIZE_SCALAR(entryPoint);
198    SERIALIZE_SCALAR(diskUnit);
199    SERIALIZE_SCALAR(diskCount);
200    SERIALIZE_SCALAR(diskPAddr);
201    SERIALIZE_SCALAR(diskBlock);
202    SERIALIZE_SCALAR(diskOperation);
203    SERIALIZE_SCALAR(outputChar);
204    SERIALIZE_SCALAR(inputChar);
205    SERIALIZE_SCALAR(bootStrapImpure);
206    SERIALIZE_SCALAR(bootStrapCPU);
207}
208
209void
210AlphaAccess::unserialize(Checkpoint *cp, const std::string &section)
211{
212    UNSERIALIZE_SCALAR(last_offset);
213    UNSERIALIZE_SCALAR(version);
214    UNSERIALIZE_SCALAR(numCPUs);
215    UNSERIALIZE_SCALAR(mem_size);
216    UNSERIALIZE_SCALAR(cpuClock);
217    UNSERIALIZE_SCALAR(intrClockFrequency);
218    UNSERIALIZE_SCALAR(kernStart);
219    UNSERIALIZE_SCALAR(kernEnd);
220    UNSERIALIZE_SCALAR(entryPoint);
221    UNSERIALIZE_SCALAR(diskUnit);
222    UNSERIALIZE_SCALAR(diskCount);
223    UNSERIALIZE_SCALAR(diskPAddr);
224    UNSERIALIZE_SCALAR(diskBlock);
225    UNSERIALIZE_SCALAR(diskOperation);
226    UNSERIALIZE_SCALAR(outputChar);
227    UNSERIALIZE_SCALAR(inputChar);
228    UNSERIALIZE_SCALAR(bootStrapImpure);
229    UNSERIALIZE_SCALAR(bootStrapCPU);
230}
231
232void
233AlphaConsole::serialize(ostream &os)
234{
235    alphaAccess->serialize(os);
236}
237
238void
239AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
240{
241    alphaAccess->unserialize(cp, section);
242}
243
244BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
245
246    SimObjectParam<SimConsole *> sim_console;
247    SimObjectParam<SimpleDisk *> disk;
248    Param<int> num_cpus;
249    SimObjectParam<MemoryController *> mmu;
250    Param<Addr> addr;
251    SimObjectParam<System *> system;
252    SimObjectParam<BaseCPU *> cpu;
253    SimObjectParam<TlaserClock *> clock;
254
255END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
256
257BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
258
259    INIT_PARAM(sim_console, "The Simulator Console"),
260    INIT_PARAM(disk, "Simple Disk"),
261    INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
262    INIT_PARAM(mmu, "Memory Controller"),
263    INIT_PARAM(addr, "Device Address"),
264    INIT_PARAM(system, "system object"),
265    INIT_PARAM(cpu, "Processor"),
266    INIT_PARAM(clock, "Turbolaser Clock")
267
268END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
269
270CREATE_SIM_OBJECT(AlphaConsole)
271{
272    return  new AlphaConsole(getInstanceName(), sim_console, disk,
273                             system, cpu, clock, num_cpus, mmu, addr);
274}
275
276REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
277