backdoor.cc revision 4762
15390SN/A/* 25443SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Nathan Binkert 295390SN/A * Ali Saidi 305390SN/A * Steve Reinhardt 315636Sgblack@eecs.umich.edu * Erik Hallnor 325636Sgblack@eecs.umich.edu */ 335390SN/A 345443SN/A/** @file 355636Sgblack@eecs.umich.edu * Alpha Console Definition 365636Sgblack@eecs.umich.edu */ 375443SN/A 385390SN/A#include <cstddef> 395390SN/A#include <string> 405390SN/A 415827Sgblack@eecs.umich.edu#include "arch/alpha/system.hh" 425636Sgblack@eecs.umich.edu#include "base/inifile.hh" 435636Sgblack@eecs.umich.edu#include "base/str.hh" 445390SN/A#include "base/trace.hh" 455636Sgblack@eecs.umich.edu#include "cpu/base.hh" 465636Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 475642Sgblack@eecs.umich.edu#include "dev/alpha/console.hh" 485642Sgblack@eecs.umich.edu#include "dev/platform.hh" 495642Sgblack@eecs.umich.edu#include "dev/simconsole.hh" 505642Sgblack@eecs.umich.edu#include "dev/simple_disk.hh" 515642Sgblack@eecs.umich.edu#include "mem/packet.hh" 525642Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 535642Sgblack@eecs.umich.edu#include "mem/physical.hh" 545642Sgblack@eecs.umich.edu#include "params/AlphaConsole.hh" 555642Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 565642Sgblack@eecs.umich.edu 575642Sgblack@eecs.umich.eduusing namespace std; 585642Sgblack@eecs.umich.eduusing namespace AlphaISA; 595642Sgblack@eecs.umich.edu 605642Sgblack@eecs.umich.eduAlphaConsole::AlphaConsole(const Params *p) 615642Sgblack@eecs.umich.edu : BasicPioDevice(p), disk(p->disk), console(p->sim_console), 625642Sgblack@eecs.umich.edu system(p->system), cpu(p->cpu) 635642Sgblack@eecs.umich.edu{ 645642Sgblack@eecs.umich.edu 655642Sgblack@eecs.umich.edu pioSize = sizeof(struct AlphaAccess); 665390SN/A 675827Sgblack@eecs.umich.edu alphaAccess = new Access(); 685642Sgblack@eecs.umich.edu alphaAccess->last_offset = pioSize - 1; 695642Sgblack@eecs.umich.edu 705390SN/A alphaAccess->version = ALPHA_ACCESS_VERSION; 715636Sgblack@eecs.umich.edu alphaAccess->diskUnit = 1; 725636Sgblack@eecs.umich.edu 735636Sgblack@eecs.umich.edu alphaAccess->diskCount = 0; 745636Sgblack@eecs.umich.edu alphaAccess->diskPAddr = 0; 755636Sgblack@eecs.umich.edu alphaAccess->diskBlock = 0; 765636Sgblack@eecs.umich.edu alphaAccess->diskOperation = 0; 775636Sgblack@eecs.umich.edu alphaAccess->outputChar = 0; 785636Sgblack@eecs.umich.edu alphaAccess->inputChar = 0; 795636Sgblack@eecs.umich.edu std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); 809808Sstever@gmail.com 815642Sgblack@eecs.umich.edu} 825636Sgblack@eecs.umich.edu 835636Sgblack@eecs.umich.eduvoid 845390SN/AAlphaConsole::startup() 855390SN/A{ 865390SN/A system->setAlphaAccess(pioAddr); 875636Sgblack@eecs.umich.edu alphaAccess->numCPUs = system->getNumCPUs(); 885636Sgblack@eecs.umich.edu alphaAccess->kernStart = system->getKernelStart(); 895636Sgblack@eecs.umich.edu alphaAccess->kernEnd = system->getKernelEnd(); 905636Sgblack@eecs.umich.edu alphaAccess->entryPoint = system->getKernelEntry(); 915636Sgblack@eecs.umich.edu alphaAccess->mem_size = system->physmem->size(); 925636Sgblack@eecs.umich.edu alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 935636Sgblack@eecs.umich.edu alphaAccess->intrClockFrequency = params()->platform->intrFrequency(); 945636Sgblack@eecs.umich.edu} 955636Sgblack@eecs.umich.edu 965636Sgblack@eecs.umich.eduTick 975636Sgblack@eecs.umich.eduAlphaConsole::read(PacketPtr pkt) 985636Sgblack@eecs.umich.edu{ 995636Sgblack@eecs.umich.edu 1005636Sgblack@eecs.umich.edu /** XXX Do we want to push the addr munging to a bus brige or something? So 1015636Sgblack@eecs.umich.edu * the device has it's physical address and then the bridge adds on whatever 1025636Sgblack@eecs.umich.edu * machine dependent address swizzle is required? 1035636Sgblack@eecs.umich.edu */ 1045636Sgblack@eecs.umich.edu 1055636Sgblack@eecs.umich.edu assert(pkt->result == Packet::Unknown); 1065636Sgblack@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1075636Sgblack@eecs.umich.edu 1085636Sgblack@eecs.umich.edu Addr daddr = pkt->getAddr() - pioAddr; 1095636Sgblack@eecs.umich.edu 1105636Sgblack@eecs.umich.edu pkt->allocate(); 1117903Shestness@cs.utexas.edu 1127903Shestness@cs.utexas.edu switch (pkt->getSize()) 1137903Shestness@cs.utexas.edu { 11410642Scdirik@micron.com case sizeof(uint32_t): 1157903Shestness@cs.utexas.edu switch (daddr) 1165390SN/A { 1175390SN/A case offsetof(AlphaAccess, last_offset): 1187811Ssteve.reinhardt@amd.com pkt->set(alphaAccess->last_offset); 1195390SN/A break; 1205390SN/A case offsetof(AlphaAccess, version): 121 pkt->set(alphaAccess->version); 122 break; 123 case offsetof(AlphaAccess, numCPUs): 124 pkt->set(alphaAccess->numCPUs); 125 break; 126 case offsetof(AlphaAccess, intrClockFrequency): 127 pkt->set(alphaAccess->intrClockFrequency); 128 break; 129 default: 130 /* Old console code read in everyting as a 32bit int 131 * we now break that for better error checking. 132 */ 133 pkt->result = Packet::BadAddress; 134 } 135 DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 136 pkt->get<uint32_t>()); 137 break; 138 case sizeof(uint64_t): 139 switch (daddr) 140 { 141 case offsetof(AlphaAccess, inputChar): 142 pkt->set(console->console_in()); 143 break; 144 case offsetof(AlphaAccess, cpuClock): 145 pkt->set(alphaAccess->cpuClock); 146 break; 147 case offsetof(AlphaAccess, mem_size): 148 pkt->set(alphaAccess->mem_size); 149 break; 150 case offsetof(AlphaAccess, kernStart): 151 pkt->set(alphaAccess->kernStart); 152 break; 153 case offsetof(AlphaAccess, kernEnd): 154 pkt->set(alphaAccess->kernEnd); 155 break; 156 case offsetof(AlphaAccess, entryPoint): 157 pkt->set(alphaAccess->entryPoint); 158 break; 159 case offsetof(AlphaAccess, diskUnit): 160 pkt->set(alphaAccess->diskUnit); 161 break; 162 case offsetof(AlphaAccess, diskCount): 163 pkt->set(alphaAccess->diskCount); 164 break; 165 case offsetof(AlphaAccess, diskPAddr): 166 pkt->set(alphaAccess->diskPAddr); 167 break; 168 case offsetof(AlphaAccess, diskBlock): 169 pkt->set(alphaAccess->diskBlock); 170 break; 171 case offsetof(AlphaAccess, diskOperation): 172 pkt->set(alphaAccess->diskOperation); 173 break; 174 case offsetof(AlphaAccess, outputChar): 175 pkt->set(alphaAccess->outputChar); 176 break; 177 default: 178 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 179 sizeof(alphaAccess->cpuStack[0]); 180 181 if (cpunum >= 0 && cpunum < 64) 182 pkt->set(alphaAccess->cpuStack[cpunum]); 183 else 184 panic("Unknown 64bit access, %#x\n", daddr); 185 } 186 DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 187 pkt->get<uint64_t>()); 188 break; 189 default: 190 pkt->result = Packet::BadAddress; 191 } 192 if (pkt->result == Packet::Unknown) 193 pkt->result = Packet::Success; 194 return pioDelay; 195} 196 197Tick 198AlphaConsole::write(PacketPtr pkt) 199{ 200 assert(pkt->result == Packet::Unknown); 201 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 202 Addr daddr = pkt->getAddr() - pioAddr; 203 204 uint64_t val = pkt->get<uint64_t>(); 205 assert(pkt->getSize() == sizeof(uint64_t)); 206 207 switch (daddr) { 208 case offsetof(AlphaAccess, diskUnit): 209 alphaAccess->diskUnit = val; 210 break; 211 212 case offsetof(AlphaAccess, diskCount): 213 alphaAccess->diskCount = val; 214 break; 215 216 case offsetof(AlphaAccess, diskPAddr): 217 alphaAccess->diskPAddr = val; 218 break; 219 220 case offsetof(AlphaAccess, diskBlock): 221 alphaAccess->diskBlock = val; 222 break; 223 224 case offsetof(AlphaAccess, diskOperation): 225 if (val == 0x13) 226 disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 227 alphaAccess->diskCount); 228 else 229 panic("Invalid disk operation!"); 230 231 break; 232 233 case offsetof(AlphaAccess, outputChar): 234 console->out((char)(val & 0xff)); 235 break; 236 237 default: 238 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 239 sizeof(alphaAccess->cpuStack[0]); 240 warn("%d: Trying to launch CPU number %d!", curTick, cpunum); 241 assert(val > 0 && "Must not access primary cpu"); 242 if (cpunum >= 0 && cpunum < 64) 243 alphaAccess->cpuStack[cpunum] = val; 244 else 245 panic("Unknown 64bit access, %#x\n", daddr); 246 } 247 248 pkt->result = Packet::Success; 249 250 return pioDelay; 251} 252 253void 254AlphaConsole::Access::serialize(ostream &os) 255{ 256 SERIALIZE_SCALAR(last_offset); 257 SERIALIZE_SCALAR(version); 258 SERIALIZE_SCALAR(numCPUs); 259 SERIALIZE_SCALAR(mem_size); 260 SERIALIZE_SCALAR(cpuClock); 261 SERIALIZE_SCALAR(intrClockFrequency); 262 SERIALIZE_SCALAR(kernStart); 263 SERIALIZE_SCALAR(kernEnd); 264 SERIALIZE_SCALAR(entryPoint); 265 SERIALIZE_SCALAR(diskUnit); 266 SERIALIZE_SCALAR(diskCount); 267 SERIALIZE_SCALAR(diskPAddr); 268 SERIALIZE_SCALAR(diskBlock); 269 SERIALIZE_SCALAR(diskOperation); 270 SERIALIZE_SCALAR(outputChar); 271 SERIALIZE_SCALAR(inputChar); 272 SERIALIZE_ARRAY(cpuStack,64); 273} 274 275void 276AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) 277{ 278 UNSERIALIZE_SCALAR(last_offset); 279 UNSERIALIZE_SCALAR(version); 280 UNSERIALIZE_SCALAR(numCPUs); 281 UNSERIALIZE_SCALAR(mem_size); 282 UNSERIALIZE_SCALAR(cpuClock); 283 UNSERIALIZE_SCALAR(intrClockFrequency); 284 UNSERIALIZE_SCALAR(kernStart); 285 UNSERIALIZE_SCALAR(kernEnd); 286 UNSERIALIZE_SCALAR(entryPoint); 287 UNSERIALIZE_SCALAR(diskUnit); 288 UNSERIALIZE_SCALAR(diskCount); 289 UNSERIALIZE_SCALAR(diskPAddr); 290 UNSERIALIZE_SCALAR(diskBlock); 291 UNSERIALIZE_SCALAR(diskOperation); 292 UNSERIALIZE_SCALAR(outputChar); 293 UNSERIALIZE_SCALAR(inputChar); 294 UNSERIALIZE_ARRAY(cpuStack, 64); 295} 296 297void 298AlphaConsole::serialize(ostream &os) 299{ 300 alphaAccess->serialize(os); 301} 302 303void 304AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) 305{ 306 alphaAccess->unserialize(cp, section); 307} 308 309AlphaConsole * 310AlphaConsoleParams::create() 311{ 312 return new AlphaConsole(this); 313} 314