backdoor.cc revision 222
19793Sakash.bagdia@arm.com/* 28706Sandreas.hansson@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 38706Sandreas.hansson@arm.com * All rights reserved. 48706Sandreas.hansson@arm.com * 58706Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68706Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78706Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98706Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118706Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128706Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 135369Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143005Sstever@eecs.umich.edu * this software without specific prior written permission. 153005Sstever@eecs.umich.edu * 163005Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173005Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183005Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193005Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203005Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213005Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223005Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233005Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243005Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253005Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263005Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273005Sstever@eecs.umich.edu */ 283005Sstever@eecs.umich.edu 293005Sstever@eecs.umich.edu/* @file 303005Sstever@eecs.umich.edu * System Console Definition 313005Sstever@eecs.umich.edu */ 323005Sstever@eecs.umich.edu 333005Sstever@eecs.umich.edu#include <cstddef> 343005Sstever@eecs.umich.edu#include <cstdio> 353005Sstever@eecs.umich.edu#include <string> 363005Sstever@eecs.umich.edu 373005Sstever@eecs.umich.edu#include "base/inifile.hh" 383005Sstever@eecs.umich.edu#include "base/str.hh" // for to_number() 393005Sstever@eecs.umich.edu#include "base/trace.hh" 403005Sstever@eecs.umich.edu#include "cpu/base_cpu.hh" 412710SN/A#include "cpu/exec_context.hh" 422710SN/A#include "dev/alpha_console.hh" 433005Sstever@eecs.umich.edu#include "dev/console.hh" 442889SN/A#include "dev/simple_disk.hh" 4512564Sgabeblack@google.com#include "dev/tlaser_clock.hh" 4612564Sgabeblack@google.com#include "mem/functional_mem/memory_control.hh" 476654Snate@binkert.org#include "sim/builder.hh" 486654Snate@binkert.org#include "sim/system.hh" 499907Snilay@cs.wisc.edu 506654Snate@binkert.orgusing namespace std; 512667SN/A 526654Snate@binkert.orgAlphaConsole::AlphaConsole(const string &name, SimConsole *cons, 536654Snate@binkert.org SimpleDisk *d, int size, System *system, 5412395Sswapnilster@gmail.com BaseCPU *cpu, TlaserClock *clock, int num_cpus, 555457Ssaidi@eecs.umich.edu Addr addr, Addr mask, MemoryController *mmu) 5611670Sandreas.hansson@arm.com : MmapDevice(name, addr, mask, mmu), disk(d), console(cons) 5711670Sandreas.hansson@arm.com{ 5811670Sandreas.hansson@arm.com consoleData = new uint8_t[size]; 598169SLisa.Hsu@amd.com memset(consoleData, 0, size); 6011682Sandreas.hansson@arm.com 6111682Sandreas.hansson@arm.com alphaAccess->last_offset = size - 1; 6211682Sandreas.hansson@arm.com alphaAccess->kernStart = system->getKernelStart(); 6311682Sandreas.hansson@arm.com alphaAccess->kernEnd = system->getKernelEnd(); 6413432Spau.cabre@metempsy.com alphaAccess->entryPoint = system->getKernelEntry(); 6511682Sandreas.hansson@arm.com 6611682Sandreas.hansson@arm.com alphaAccess->version = ALPHA_ACCESS_VERSION; 6711682Sandreas.hansson@arm.com alphaAccess->numCPUs = num_cpus; 683394Shsul@eecs.umich.edu alphaAccess->mem_size = system->physmem->getSize(); 699197Snilay@cs.wisc.edu alphaAccess->cpuClock = cpu->getFreq() / 1000000; 709197Snilay@cs.wisc.edu alphaAccess->intrClockFrequency = clock->frequency(); 719197Snilay@cs.wisc.edu 729197Snilay@cs.wisc.edu alphaAccess->diskUnit = 1; 739197Snilay@cs.wisc.edu} 749197Snilay@cs.wisc.edu 759197Snilay@cs.wisc.eduFault 769197Snilay@cs.wisc.eduAlphaConsole::read(MemReqPtr req, uint8_t *data) 779197Snilay@cs.wisc.edu{ 789197Snilay@cs.wisc.edu memset(data, 0, req->size); 799197Snilay@cs.wisc.edu 809197Snilay@cs.wisc.edu if (req->size == sizeof(uint32_t)) { 819197Snilay@cs.wisc.edu Addr daddr = req->paddr & addr_mask; 829197Snilay@cs.wisc.edu *(uint32_t *)data = *(uint32_t *)(consoleData + daddr); 839197Snilay@cs.wisc.edu 849197Snilay@cs.wisc.edu#if 0 859197Snilay@cs.wisc.edu DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", 869197Snilay@cs.wisc.edu daddr, *(uint32_t *)data); 879197Snilay@cs.wisc.edu#endif 889197Snilay@cs.wisc.edu } 899197Snilay@cs.wisc.edu 9012146Spau.cabre@metempsy.com return No_Fault; 919197Snilay@cs.wisc.edu} 929907Snilay@cs.wisc.edu 939197Snilay@cs.wisc.eduFault 9410803Sbrandon.potter@amd.comAlphaConsole::write(MemReqPtr req, const uint8_t *data) 9510803Sbrandon.potter@amd.com{ 9610803Sbrandon.potter@amd.com uint64_t val; 9710803Sbrandon.potter@amd.com 989197Snilay@cs.wisc.edu switch (req->size) { 999217Snilay@cs.wisc.edu case sizeof(uint32_t): 1009197Snilay@cs.wisc.edu val = *(uint32_t *)data; 1019197Snilay@cs.wisc.edu break; 1029197Snilay@cs.wisc.edu case sizeof(uint64_t): 1039197Snilay@cs.wisc.edu val = *(uint64_t *)data; 1049197Snilay@cs.wisc.edu break; 1059197Snilay@cs.wisc.edu default: 1069197Snilay@cs.wisc.edu return Machine_Check_Fault; 1079197Snilay@cs.wisc.edu } 1089197Snilay@cs.wisc.edu 1099197Snilay@cs.wisc.edu Addr paddr = req->paddr & addr_mask; 1109197Snilay@cs.wisc.edu 1119197Snilay@cs.wisc.edu if (paddr == offsetof(AlphaAccess, diskUnit)) { 1129197Snilay@cs.wisc.edu alphaAccess->diskUnit = val; 1139197Snilay@cs.wisc.edu return No_Fault; 11412014Sgabeblack@google.com } 1159197Snilay@cs.wisc.edu 1169197Snilay@cs.wisc.edu if (paddr == offsetof(AlphaAccess, diskCount)) { 1179197Snilay@cs.wisc.edu alphaAccess->diskCount = val; 1189197Snilay@cs.wisc.edu return No_Fault; 1199197Snilay@cs.wisc.edu } 1202957SN/A 1218920Snilay@cs.wisc.edu if (paddr == offsetof(AlphaAccess, diskPAddr)) { 1228920Snilay@cs.wisc.edu alphaAccess->diskPAddr = val; 1232957SN/A return No_Fault; 1248862Snilay@cs.wisc.edu } 1258862Snilay@cs.wisc.edu 1268467Snilay@cs.wisc.edu if (paddr == offsetof(AlphaAccess, diskBlock)) { 1272957SN/A alphaAccess->diskBlock = val; 1282957SN/A return No_Fault; 1292957SN/A } 13012564Sgabeblack@google.com 1312957SN/A if (paddr == offsetof(AlphaAccess, diskOperation)) { 1322957SN/A if (val == 0x13) 1338167SLisa.Hsu@amd.com disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 1349197Snilay@cs.wisc.edu alphaAccess->diskCount); 1358167SLisa.Hsu@amd.com else 1365369Ssaidi@eecs.umich.edu panic("Invalid disk operation!"); 1378167SLisa.Hsu@amd.com 1388167SLisa.Hsu@amd.com return No_Fault; 13912564Sgabeblack@google.com } 1408167SLisa.Hsu@amd.com 1418167SLisa.Hsu@amd.com if (paddr == offsetof(AlphaAccess, outputChar)) { 1428167SLisa.Hsu@amd.com console->out((char)(val & 0xff), false); 1438167SLisa.Hsu@amd.com return No_Fault; 1448168SLisa.Hsu@amd.com } 14510037SARM gem5 Developers 14610037SARM gem5 Developers if (paddr == offsetof(AlphaAccess, bootStrapImpure)) { 14710037SARM gem5 Developers alphaAccess->bootStrapImpure = val; 14810037SARM gem5 Developers return No_Fault; 14910037SARM gem5 Developers } 1508168SLisa.Hsu@amd.com 15110037SARM gem5 Developers if (paddr == offsetof(AlphaAccess, bootStrapCPU)) { 15210037SARM gem5 Developers warn("%d: Trying to launch another CPU!", curTick); 15311851Sbrandon.potter@amd.com int cpu = val; 1548167SLisa.Hsu@amd.com assert(cpu > 0 && "Must not access primary cpu"); 15512564Sgabeblack@google.com 15612564Sgabeblack@google.com ExecContext *other_xc = req->xc->system->execContexts[cpu]; 15712564Sgabeblack@google.com other_xc->regs.intRegFile[16] = cpu; 1585369Ssaidi@eecs.umich.edu other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu; 1598920Snilay@cs.wisc.edu other_xc->regs.intRegFile[0] = cpu; 1609197Snilay@cs.wisc.edu other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; 1618920Snilay@cs.wisc.edu other_xc->setStatus(ExecContext::Active); //Start the cpu 16212564Sgabeblack@google.com return No_Fault; 1638920Snilay@cs.wisc.edu } 1645369Ssaidi@eecs.umich.edu 1655369Ssaidi@eecs.umich.edu return No_Fault; 1668718Snilay@cs.wisc.edu} 1679197Snilay@cs.wisc.edu 1689197Snilay@cs.wisc.eduvoid 1699197Snilay@cs.wisc.eduAlphaAccess::serialize(ostream &os) 1709197Snilay@cs.wisc.edu{ 1719197Snilay@cs.wisc.edu SERIALIZE_SCALAR(last_offset); 1723005Sstever@eecs.umich.edu SERIALIZE_SCALAR(version); 1733395Shsul@eecs.umich.edu SERIALIZE_SCALAR(numCPUs); 1743395Shsul@eecs.umich.edu SERIALIZE_SCALAR(mem_size); 1759793Sakash.bagdia@arm.com SERIALIZE_SCALAR(cpuClock); 1769836Sandreas.hansson@arm.com SERIALIZE_SCALAR(intrClockFrequency); 1779815SAndreas Hansson <andreas.hansson> SERIALIZE_SCALAR(kernStart); 1789793Sakash.bagdia@arm.com SERIALIZE_SCALAR(kernEnd); 17911147Smitch.hayenga@arm.com SERIALIZE_SCALAR(entryPoint); 18011147Smitch.hayenga@arm.com SERIALIZE_SCALAR(diskUnit); 18111147Smitch.hayenga@arm.com SERIALIZE_SCALAR(diskCount); 1829827Sakash.bagdia@arm.com SERIALIZE_SCALAR(diskPAddr); 1839827Sakash.bagdia@arm.com SERIALIZE_SCALAR(diskBlock); 1849827Sakash.bagdia@arm.com SERIALIZE_SCALAR(diskOperation); 1859827Sakash.bagdia@arm.com SERIALIZE_SCALAR(outputChar); 1869827Sakash.bagdia@arm.com SERIALIZE_SCALAR(bootStrapImpure); 1879827Sakash.bagdia@arm.com SERIALIZE_SCALAR(bootStrapCPU); 1889827Sakash.bagdia@arm.com} 1899827Sakash.bagdia@arm.com 1909827Sakash.bagdia@arm.comvoid 1919827Sakash.bagdia@arm.comAlphaAccess::unserialize(const IniFile *db, const std::string §ion) 1929793Sakash.bagdia@arm.com{ 1939827Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(last_offset); 1949827Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(version); 1959827Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(numCPUs); 1969793Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(mem_size); 19711251Sradhika.jagtap@ARM.com UNSERIALIZE_SCALAR(cpuClock); 19811251Sradhika.jagtap@ARM.com UNSERIALIZE_SCALAR(intrClockFrequency); 19911251Sradhika.jagtap@ARM.com UNSERIALIZE_SCALAR(kernStart); 20011251Sradhika.jagtap@ARM.com UNSERIALIZE_SCALAR(kernEnd); 20111251Sradhika.jagtap@ARM.com UNSERIALIZE_SCALAR(entryPoint); 2029793Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(diskUnit); 2039793Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(diskCount); 2049793Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(diskPAddr); 2059793Sakash.bagdia@arm.com UNSERIALIZE_SCALAR(diskBlock); 2063395Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(diskOperation); 20712941Sandreas.sandberg@arm.com UNSERIALIZE_SCALAR(outputChar); 20810555Salexandru.dutu@amd.com UNSERIALIZE_SCALAR(bootStrapImpure); 20911839SCurtis.Dunham@arm.com UNSERIALIZE_SCALAR(bootStrapCPU); 21010555Salexandru.dutu@amd.com} 21110555Salexandru.dutu@amd.com 21210555Salexandru.dutu@amd.comvoid 21310555Salexandru.dutu@amd.comAlphaConsole::serialize(ostream &os) 21410555Salexandru.dutu@amd.com{ 21510555Salexandru.dutu@amd.com alphaAccess->serialize(os); 2168926Sandreas.hansson@arm.com} 2179647Sdam.sunwoo@arm.com 21813684Sgiacomo.travaglini@arm.comvoid 21913012Sandreas.sandberg@arm.comAlphaConsole::unserialize(const IniFile *db, const std::string §ion) 2209647Sdam.sunwoo@arm.com{ 2219647Sdam.sunwoo@arm.com alphaAccess->unserialize(db, section); 2229647Sdam.sunwoo@arm.com} 2233395Shsul@eecs.umich.edu 2249197Snilay@cs.wisc.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 2259197Snilay@cs.wisc.edu 2269197Snilay@cs.wisc.edu SimObjectParam<SimConsole *> sim_console; 2278957Sjayneel@cs.wisc.edu SimObjectParam<SimpleDisk *> disk; 2288957Sjayneel@cs.wisc.edu Param<int> size; 2298957Sjayneel@cs.wisc.edu Param<int> num_cpus; 2303005Sstever@eecs.umich.edu SimObjectParam<MemoryController *> mmu; 2319647Sdam.sunwoo@arm.com Param<Addr> addr; 23210381Sdam.sunwoo@arm.com Param<Addr> mask; 2339647Sdam.sunwoo@arm.com SimObjectParam<System *> system; 2348887Sgeoffrey.blake@arm.com SimObjectParam<BaseCPU *> cpu; 2358887Sgeoffrey.blake@arm.com SimObjectParam<TlaserClock *> clock; 2368887Sgeoffrey.blake@arm.com 23713432Spau.cabre@metempsy.comEND_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 23813432Spau.cabre@metempsy.com 23913432Spau.cabre@metempsy.comBEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 24013432Spau.cabre@metempsy.com 2419384SAndreas.Sandberg@arm.com INIT_PARAM(sim_console, "The Simulator Console"), 2429384SAndreas.Sandberg@arm.com INIT_PARAM(disk, "Simple Disk"), 2438887Sgeoffrey.blake@arm.com INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)), 24410519Snilay@cs.wisc.edu INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1), 24510120Snilay@cs.wisc.edu INIT_PARAM(mmu, "Memory Controller"), 2468896Snilay@cs.wisc.edu INIT_PARAM(addr, "Device Address"), 24710300Scastilloe@unican.es INIT_PARAM(mask, "Address Mask"), 24810300Scastilloe@unican.es INIT_PARAM(system, "system object"), 2498896Snilay@cs.wisc.edu INIT_PARAM(cpu, "Processor"), 25010120Snilay@cs.wisc.edu INIT_PARAM(clock, "Turbolaser Clock") 2518896Snilay@cs.wisc.edu 2528896Snilay@cs.wisc.eduEND_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 2539268Smalek.musleh@gmail.com 2549268Smalek.musleh@gmail.comCREATE_SIM_OBJECT(AlphaConsole) 2558896Snilay@cs.wisc.edu{ 2568896Snilay@cs.wisc.edu return new AlphaConsole(getInstanceName(), sim_console, 2578896Snilay@cs.wisc.edu disk, size, system, 2588896Snilay@cs.wisc.edu cpu, clock, num_cpus, 2598896Snilay@cs.wisc.edu addr, mask, mmu); 2609222Shestness@cs.wisc.edu} 26111150Smitch.hayenga@arm.com 26211150Smitch.hayenga@arm.comREGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 26311150Smitch.hayenga@arm.com