backdoor.cc revision 146
110816SN/A/* 29288SN/A * Copyright (c) 2003 The Regents of The University of Michigan 39288SN/A * All rights reserved. 49288SN/A * 59288SN/A * Redistribution and use in source and binary forms, with or without 69288SN/A * modification, are permitted provided that the following conditions are 79288SN/A * met: redistributions of source code must retain the above copyright 89288SN/A * notice, this list of conditions and the following disclaimer; 99288SN/A * redistributions in binary form must reproduce the above copyright 109288SN/A * notice, this list of conditions and the following disclaimer in the 119288SN/A * documentation and/or other materials provided with the distribution; 129288SN/A * neither the name of the copyright holders nor the names of its 134486SN/A * contributors may be used to endorse or promote products derived from 144486SN/A * this software without specific prior written permission. 154486SN/A * 164486SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486SN/A */ 284486SN/A 294486SN/A/* @file 304486SN/A * System Console Definition 314486SN/A */ 324486SN/A 334486SN/A#include <cstddef> 344486SN/A#include <cstdio> 354486SN/A#include <string> 364486SN/A 374486SN/A#include "base/inifile.hh" 384486SN/A#include "base/str.hh" // for to_number() 394486SN/A#include "base/trace.hh" 4011053Sandreas.hansson@arm.com#include "cpu/base_cpu.hh" 414486SN/A#include "cpu/exec_context.hh" 423102SN/A#include "dev/alpha_console.hh" 438833SN/A#include "dev/console.hh" 442826SN/A#include "dev/simple_disk.hh" 458831SN/A#include "dev/tlaser_clock.hh" 469796SN/A#include "mem/functional_mem/memory_control.hh" 471615SN/A#include "sim/builder.hh" 482826SN/A#include "sim/system.hh" 491366SN/A 5011053Sandreas.hansson@arm.comusing namespace std; 519338SN/A 5210816SN/AAlphaConsole::AlphaConsole(const string &name, SimConsole *cons, 5310816SN/A SimpleDisk *d, int size, System *system, 5410816SN/A BaseCPU *cpu, TlaserClock *clock, int num_cpus, 5510816SN/A Addr addr, Addr mask, MemoryController *mmu) 5610816SN/A : MmapDevice(name, addr, mask, mmu), disk(d), console(cons) 5710816SN/A{ 5810816SN/A consoleData = new uint8_t[size]; 591310SN/A memset(consoleData, 0, size); 6010816SN/A 6110816SN/A alphaAccess->last_offset = size - 1; 6210816SN/A alphaAccess->kernStart = system->getKernelStart(); 6310816SN/A alphaAccess->kernEnd = system->getKernelEnd(); 6410816SN/A alphaAccess->entryPoint = system->getKernelEntry(); 6510816SN/A 6610816SN/A alphaAccess->version = ALPHA_ACCESS_VERSION; 676122SN/A alphaAccess->numCPUs = num_cpus; 6810816SN/A alphaAccess->mem_size = system->physmem->getSize(); 6910884SN/A alphaAccess->cpuClock = cpu->getFreq() / 1000000; 7010816SN/A alphaAccess->intrClockFrequency = clock->frequency(); 7110816SN/A 725875SN/A alphaAccess->diskUnit = 1; 7310816SN/A} 7410816SN/A 7510816SN/AFault 7610025SN/AAlphaConsole::read(MemReqPtr req, uint8_t *data) 7710025SN/A{ 7810816SN/A memset(data, 0, req->size); 7910816SN/A 8010816SN/A if (req->size == sizeof(uint32_t)) { 8110816SN/A Addr daddr = req->paddr & addr_mask; 8210816SN/A *(uint32_t *)data = *(uint32_t *)(consoleData + daddr); 8310816SN/A 8410816SN/A#if 0 8510816SN/A DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", 8611053Sandreas.hansson@arm.com daddr, *(uint32_t *)data); 8711197Sandreas.hansson@arm.com#endif 8811197Sandreas.hansson@arm.com } 8911197Sandreas.hansson@arm.com 9011197Sandreas.hansson@arm.com return No_Fault; 9111053Sandreas.hansson@arm.com} 9211053Sandreas.hansson@arm.com 9311053Sandreas.hansson@arm.comFault 9411197Sandreas.hansson@arm.comAlphaConsole::write(MemReqPtr req, const uint8_t *data) 9511197Sandreas.hansson@arm.com{ 9611197Sandreas.hansson@arm.com uint64_t val; 9711197Sandreas.hansson@arm.com 9811197Sandreas.hansson@arm.com switch (req->size) { 9911197Sandreas.hansson@arm.com case sizeof(uint32_t): 10011197Sandreas.hansson@arm.com val = *(uint32_t *)data; 10111197Sandreas.hansson@arm.com break; 10211197Sandreas.hansson@arm.com case sizeof(uint64_t): 10311197Sandreas.hansson@arm.com val = *(uint64_t *)data; 10411197Sandreas.hansson@arm.com break; 10511197Sandreas.hansson@arm.com default: 10611199Sandreas.hansson@arm.com return Machine_Check_Fault; 10711199Sandreas.hansson@arm.com } 10811199Sandreas.hansson@arm.com 10911199Sandreas.hansson@arm.com Addr paddr = req->paddr & addr_mask; 11011199Sandreas.hansson@arm.com 11111199Sandreas.hansson@arm.com if (paddr == offsetof(AlphaAccess, diskUnit)) { 11211199Sandreas.hansson@arm.com alphaAccess->diskUnit = val; 11311199Sandreas.hansson@arm.com return No_Fault; 114 } 115 116 if (paddr == offsetof(AlphaAccess, diskCount)) { 117 alphaAccess->diskCount = val; 118 return No_Fault; 119 } 120 121 if (paddr == offsetof(AlphaAccess, diskPAddr)) { 122 alphaAccess->diskPAddr = val; 123 return No_Fault; 124 } 125 126 if (paddr == offsetof(AlphaAccess, diskBlock)) { 127 alphaAccess->diskBlock = val; 128 return No_Fault; 129 } 130 131 if (paddr == offsetof(AlphaAccess, diskOperation)) { 132 if (val == 0x13) 133 disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 134 alphaAccess->diskCount); 135 else 136 panic("Invalid disk operation!"); 137 138 return No_Fault; 139 } 140 141 if (paddr == offsetof(AlphaAccess, outputChar)) { 142 console->out((char)(val & 0xff), false); 143 return No_Fault; 144 } 145 146 if (paddr == offsetof(AlphaAccess, bootStrapImpure)) { 147 alphaAccess->bootStrapImpure = val; 148 return No_Fault; 149 } 150 151 if (paddr == offsetof(AlphaAccess, bootStrapCPU)) { 152 warn("%d: Trying to launch another CPU!", curTick); 153 int cpu = val; 154 assert(cpu > 0 && "Must not access primary cpu"); 155 156 ExecContext *other_xc = req->xc->system->xcvec[cpu]; 157 other_xc->regs.intRegFile[16] = cpu; 158 other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu; 159 other_xc->regs.intRegFile[0] = cpu; 160 other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; 161 other_xc->setStatus(ExecContext::Active); //Start the cpu 162 return No_Fault; 163 } 164 165 return No_Fault; 166} 167 168void 169AlphaConsole::serialize() 170{ 171 nameOut(); 172 // assumes full AlphaAccess size 173 // might have unnecessary fields here 174 paramOut("last_offset",alphaAccess->last_offset); 175 paramOut("version",alphaAccess->version); 176 paramOut("numCPUs",alphaAccess->numCPUs); 177 paramOut("mem_size",alphaAccess->mem_size); 178 paramOut("cpuClock",alphaAccess->cpuClock); 179 paramOut("intrClockFrequency",alphaAccess->intrClockFrequency); 180 paramOut("kernStart",alphaAccess->kernStart); 181 paramOut("kernEnd",alphaAccess->kernEnd); 182 paramOut("entryPoint",alphaAccess->entryPoint); 183 paramOut("diskUnit",alphaAccess->diskUnit); 184 paramOut("diskCount",alphaAccess->diskCount); 185 paramOut("diskPAddr",alphaAccess->diskPAddr); 186 paramOut("diskBlock",alphaAccess->diskBlock); 187 paramOut("diskOperation",alphaAccess->diskOperation); 188 paramOut("outputChar",alphaAccess->outputChar); 189 paramOut("bootStrapImpure",alphaAccess->bootStrapImpure); 190 paramOut("bootStrapCPU",alphaAccess->bootStrapCPU); 191} 192 193void 194AlphaConsole::unserialize(IniFile &db, const std::string &category, 195 ConfigNode *node) 196{ 197 string data; 198 db.findDefault(category,"last_offset",data); 199 to_number(data,alphaAccess->last_offset); 200 db.findDefault(category,"version",data); 201 to_number(data,alphaAccess->version); 202 db.findDefault(category,"numCPUs",data); 203 to_number(data,alphaAccess->numCPUs); 204 db.findDefault(category,"mem_size",data); 205 to_number(data,alphaAccess->mem_size); 206 db.findDefault(category,"cpuClock",data); 207 to_number(data,alphaAccess->cpuClock); 208 db.findDefault(category,"intrClockFrequency",data); 209 to_number(data,alphaAccess->intrClockFrequency); 210 db.findDefault(category,"kernStart",data); 211 to_number(data,alphaAccess->kernStart); 212 db.findDefault(category,"kernEnd",data); 213 to_number(data,alphaAccess->kernEnd); 214 db.findDefault(category,"entryPoint",data); 215 to_number(data,alphaAccess->entryPoint); 216 db.findDefault(category,"diskUnit",data); 217 to_number(data,alphaAccess->diskUnit); 218 db.findDefault(category,"diskCount",data); 219 to_number(data,alphaAccess->diskCount); 220 db.findDefault(category,"diskPAddr",data); 221 to_number(data,alphaAccess->diskPAddr); 222 db.findDefault(category,"diskBlock",data); 223 to_number(data,alphaAccess->diskBlock); 224 db.findDefault(category,"diskOperation",data); 225 to_number(data,alphaAccess->diskOperation); 226 db.findDefault(category,"outputChar",data); 227 to_number(data,alphaAccess->outputChar); 228 db.findDefault(category,"bootStrapImpure",data); 229 to_number(data,alphaAccess->bootStrapImpure); 230 db.findDefault(category,"bootStrapCPU",data); 231 to_number(data,alphaAccess->bootStrapCPU); 232 233} 234 235BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 236 237 SimObjectParam<SimConsole *> sim_console; 238 SimObjectParam<SimpleDisk *> disk; 239 Param<int> size; 240 Param<int> num_cpus; 241 SimObjectParam<MemoryController *> mmu; 242 Param<Addr> addr; 243 Param<Addr> mask; 244 SimObjectParam<System *> system; 245 SimObjectParam<BaseCPU *> cpu; 246 SimObjectParam<TlaserClock *> clock; 247 248END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 249 250BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 251 252 INIT_PARAM(sim_console, "The Simulator Console"), 253 INIT_PARAM(disk, "Simple Disk"), 254 INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)), 255 INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1), 256 INIT_PARAM(mmu, "Memory Controller"), 257 INIT_PARAM(addr, "Device Address"), 258 INIT_PARAM(mask, "Address Mask"), 259 INIT_PARAM(system, "system object"), 260 INIT_PARAM(cpu, "Processor"), 261 INIT_PARAM(clock, "Turbolaser Clock") 262 263END_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 264 265CREATE_SIM_OBJECT(AlphaConsole) 266{ 267 return new AlphaConsole(getInstanceName(), sim_console, 268 disk, size, system, 269 cpu, clock, num_cpus, 270 addr, mask, mmu); 271} 272 273REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 274