thread_context.hh revision 2972
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/types.hh" 352972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 362972Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 371858SN/A#include "config/full_system.hh" 382423SN/A#include "mem/request.hh" 392190SN/A#include "sim/faults.hh" 4056SN/A#include "sim/host.hh" 41217SN/A#include "sim/serialize.hh" 422036SN/A#include "sim/byteswap.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 462190SN/Aclass AlphaDTB; 472190SN/Aclass AlphaITB; 482190SN/Aclass BaseCPU; 492313SN/Aclass EndQuiesceEvent; 502235SN/Aclass Event; 512423SN/Aclass TranslatingPort; 522521SN/Aclass FunctionalPort; 532521SN/Aclass VirtualPort; 542190SN/Aclass Process; 552190SN/Aclass System; 562330SN/Anamespace Kernel { 572330SN/A class Statistics; 582330SN/A}; 592SN/A 602680Sktlim@umich.edu/** 612680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 622680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 632680Sktlim@umich.edu * state that might be needed by external objects, ranging from 642680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 652680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 662680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 672680Sktlim@umich.edu * 682680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 692680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 702680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 712682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 722680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 732680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 742680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 752680Sktlim@umich.edu */ 762680Sktlim@umich.educlass ThreadContext 772SN/A{ 782107SN/A protected: 792107SN/A typedef TheISA::RegFile RegFile; 802107SN/A typedef TheISA::MachInst MachInst; 812190SN/A typedef TheISA::IntReg IntReg; 822455SN/A typedef TheISA::FloatReg FloatReg; 832455SN/A typedef TheISA::FloatRegBits FloatRegBits; 842107SN/A typedef TheISA::MiscRegFile MiscRegFile; 852159SN/A typedef TheISA::MiscReg MiscReg; 862SN/A public: 87246SN/A enum Status 88246SN/A { 89246SN/A /// Initialized but not running yet. All CPUs start in 90246SN/A /// this state, but most transition to Active on cycle 1. 91246SN/A /// In MP or SMT systems, non-primary contexts will stay 92246SN/A /// in this state until a thread is assigned to them. 93246SN/A Unallocated, 94246SN/A 95246SN/A /// Running. Instructions should be executed only when 96246SN/A /// the context is in this state. 97246SN/A Active, 98246SN/A 99246SN/A /// Temporarily inactive. Entered while waiting for 1002190SN/A /// synchronization, etc. 101246SN/A Suspended, 102246SN/A 103246SN/A /// Permanently shut down. Entered when target executes 104246SN/A /// m5exit pseudo-instruction. When all contexts enter 105246SN/A /// this state, the simulation will terminate. 106246SN/A Halted 107246SN/A }; 1082SN/A 1092680Sktlim@umich.edu virtual ~ThreadContext() { }; 1102423SN/A 1112190SN/A virtual BaseCPU *getCpuPtr() = 0; 112180SN/A 1132190SN/A virtual void setCpuId(int id) = 0; 1142190SN/A 1152190SN/A virtual int readCpuId() = 0; 1162190SN/A 1172190SN/A#if FULL_SYSTEM 1182190SN/A virtual System *getSystemPtr() = 0; 1192190SN/A 1202190SN/A virtual AlphaITB *getITBPtr() = 0; 1212190SN/A 1222190SN/A virtual AlphaDTB * getDTBPtr() = 0; 1232521SN/A 1242330SN/A virtual Kernel::Statistics *getKernelStats() = 0; 1252654SN/A 1262521SN/A virtual FunctionalPort *getPhysPort() = 0; 1272521SN/A 1282680Sktlim@umich.edu virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 1292521SN/A 1302521SN/A virtual void delVirtPort(VirtualPort *vp) = 0; 1312190SN/A#else 1322518SN/A virtual TranslatingPort *getMemPort() = 0; 1332518SN/A 1342190SN/A virtual Process *getProcessPtr() = 0; 1352190SN/A#endif 1362190SN/A 1372190SN/A virtual Status status() const = 0; 1382159SN/A 1392235SN/A virtual void setStatus(Status new_status) = 0; 1402103SN/A 141393SN/A /// Set the status to Active. Optional delay indicates number of 142393SN/A /// cycles to wait before beginning execution. 1432190SN/A virtual void activate(int delay = 1) = 0; 144393SN/A 145393SN/A /// Set the status to Suspended. 1462190SN/A virtual void suspend() = 0; 147393SN/A 148393SN/A /// Set the status to Unallocated. 1492875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 150393SN/A 151393SN/A /// Set the status to Halted. 1522190SN/A virtual void halt() = 0; 1532159SN/A 1542159SN/A#if FULL_SYSTEM 1552190SN/A virtual void dumpFuncProfile() = 0; 1562159SN/A#endif 1572159SN/A 1582680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1592159SN/A 1602190SN/A virtual void regStats(const std::string &name) = 0; 1612159SN/A 1622190SN/A virtual void serialize(std::ostream &os) = 0; 1632190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1642159SN/A 1652235SN/A#if FULL_SYSTEM 1662313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1672235SN/A 1682235SN/A // Not necessarily the best location for these... 1692235SN/A // Having an extra function just to read these is obnoxious 1702235SN/A virtual Tick readLastActivate() = 0; 1712235SN/A virtual Tick readLastSuspend() = 0; 1722254SN/A 1732254SN/A virtual void profileClear() = 0; 1742254SN/A virtual void profileSample() = 0; 1752235SN/A#endif 1762235SN/A 1772190SN/A virtual int getThreadNum() = 0; 1782159SN/A 1792235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1802254SN/A // However, may be quite useful in SPARC. 1812190SN/A virtual TheISA::MachInst getInst() = 0; 1822159SN/A 1832680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1842159SN/A 1852190SN/A virtual void clearArchRegs() = 0; 1862159SN/A 1872159SN/A // 1882159SN/A // New accessors for new decoder. 1892159SN/A // 1902190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1912159SN/A 1922455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1932159SN/A 1942455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1952159SN/A 1962455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 1972455SN/A 1982455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1992159SN/A 2002190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2012159SN/A 2022455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2032159SN/A 2042455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2052159SN/A 2062455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2072455SN/A 2082455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2092159SN/A 2102190SN/A virtual uint64_t readPC() = 0; 2112159SN/A 2122190SN/A virtual void setPC(uint64_t val) = 0; 2132159SN/A 2142190SN/A virtual uint64_t readNextPC() = 0; 2152159SN/A 2162190SN/A virtual void setNextPC(uint64_t val) = 0; 2172159SN/A 2182447SN/A virtual uint64_t readNextNPC() = 0; 2192447SN/A 2202447SN/A virtual void setNextNPC(uint64_t val) = 0; 2212447SN/A 2222190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2232159SN/A 2242190SN/A virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 2252190SN/A 2262190SN/A virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 2272190SN/A 2282190SN/A virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 2292190SN/A 2302235SN/A // Also not necessarily the best location for these two. Hopefully will go 2312235SN/A // away once we decide upon where st cond failures goes. 2322190SN/A virtual unsigned readStCondFailures() = 0; 2332190SN/A 2342190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2352159SN/A 2362159SN/A#if FULL_SYSTEM 2372190SN/A virtual bool inPalMode() = 0; 2382159SN/A#endif 2392159SN/A 2402235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2412190SN/A virtual bool misspeculating() = 0; 2422190SN/A 2432159SN/A#if !FULL_SYSTEM 2442190SN/A virtual IntReg getSyscallArg(int i) = 0; 2452159SN/A 2462159SN/A // used to shift args for indirect syscall 2472190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2482159SN/A 2492190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2502159SN/A 2512235SN/A // Same with st cond failures. 2522190SN/A virtual Counter readFuncExeInst() = 0; 2532834Sksewell@umich.edu 2542834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2552834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2562834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2572834Sksewell@umich.edu virtual int exit() { return 1; }; 2582159SN/A#endif 2592525SN/A 2602972Sgblack@eecs.umich.edu virtual void changeRegFileContext(TheISA::RegContextParam param, 2612972Sgblack@eecs.umich.edu TheISA::RegContextVal val) = 0; 2622159SN/A}; 2632159SN/A 2642682Sktlim@umich.edu/** 2652682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2662682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2672682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2682682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2692682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2702682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2712682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2722682Sktlim@umich.edu * simple_thread.hh for an example of this. 2732682Sktlim@umich.edu */ 2742680Sktlim@umich.edutemplate <class TC> 2752680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2762190SN/A{ 2772190SN/A public: 2782680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2792680Sktlim@umich.edu { actualTC = actual_tc; } 2802159SN/A 2812190SN/A private: 2822680Sktlim@umich.edu TC *actualTC; 2832SN/A 2842SN/A public: 2852SN/A 2862680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2872SN/A 2882680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 289716SN/A 2902680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 2912SN/A 2921858SN/A#if FULL_SYSTEM 2932680Sktlim@umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2942SN/A 2952680Sktlim@umich.edu AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 2961917SN/A 2972680Sktlim@umich.edu AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 2982521SN/A 2992680Sktlim@umich.edu Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 3002654SN/A 3012680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3022521SN/A 3032680Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 3042521SN/A 3052680Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 3062SN/A#else 3072680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3082518SN/A 3092680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3102SN/A#endif 3112SN/A 3122680Sktlim@umich.edu Status status() const { return actualTC->status(); } 313595SN/A 3142680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3152SN/A 3162190SN/A /// Set the status to Active. Optional delay indicates number of 3172190SN/A /// cycles to wait before beginning execution. 3182680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3192SN/A 3202190SN/A /// Set the status to Suspended. 3212680Sktlim@umich.edu void suspend() { actualTC->suspend(); } 3222SN/A 3232190SN/A /// Set the status to Unallocated. 3242875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3252SN/A 3262190SN/A /// Set the status to Halted. 3272680Sktlim@umich.edu void halt() { actualTC->halt(); } 328217SN/A 3291858SN/A#if FULL_SYSTEM 3302680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3312190SN/A#endif 3322190SN/A 3332680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3342680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3352190SN/A 3362680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3372190SN/A 3382680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3392190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3402680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3412190SN/A 3422235SN/A#if FULL_SYSTEM 3432680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3442235SN/A 3452680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3462680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3472254SN/A 3482680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3492680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3502235SN/A#endif 3512235SN/A 3522680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3532190SN/A 3542190SN/A // @todo: Do I need this? 3552680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3562SN/A 3572190SN/A // @todo: Do I need this? 3582680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3592SN/A 3602680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 361716SN/A 3622SN/A // 3632SN/A // New accessors for new decoder. 3642SN/A // 3652SN/A uint64_t readIntReg(int reg_idx) 3662680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3672SN/A 3682455SN/A FloatReg readFloatReg(int reg_idx, int width) 3692680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3702SN/A 3712455SN/A FloatReg readFloatReg(int reg_idx) 3722680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3732SN/A 3742455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3752680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3762455SN/A 3772455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3782680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3792SN/A 3802SN/A void setIntReg(int reg_idx, uint64_t val) 3812680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3822SN/A 3832455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3842680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3852SN/A 3862455SN/A void setFloatReg(int reg_idx, FloatReg val) 3872680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3882SN/A 3892455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 3902680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 3912455SN/A 3922455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3932680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3942SN/A 3952680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 3962SN/A 3972680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 3982206SN/A 3992680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4002252SN/A 4012680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4022SN/A 4032680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4042447SN/A 4052680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4062447SN/A 4072159SN/A MiscReg readMiscReg(int misc_reg) 4082680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4092SN/A 4102159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 4112680Sktlim@umich.edu { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 4122SN/A 4132159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 4142680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4152SN/A 4162159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 4172680Sktlim@umich.edu { return actualTC->setMiscRegWithEffect(misc_reg, val); } 4182190SN/A 4192190SN/A unsigned readStCondFailures() 4202680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4212190SN/A 4222190SN/A void setStCondFailures(unsigned sc_failures) 4232680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4241858SN/A#if FULL_SYSTEM 4252680Sktlim@umich.edu bool inPalMode() { return actualTC->inPalMode(); } 4262SN/A#endif 4272SN/A 4282190SN/A // @todo: Fix this! 4292680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4302190SN/A 4311858SN/A#if !FULL_SYSTEM 4322680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 433360SN/A 434360SN/A // used to shift args for indirect syscall 4352190SN/A void setSyscallArg(int i, IntReg val) 4362680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 437360SN/A 4381450SN/A void setSyscallReturn(SyscallReturn return_value) 4392680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 440360SN/A 4412680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4422SN/A#endif 4432525SN/A 4442972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4452972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4462525SN/A { 4472680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4482525SN/A } 4492SN/A}; 4502SN/A 4512190SN/A#endif 452