thread_context.hh revision 2972
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/types.hh" 35#include "arch/regfile.hh" 36#include "arch/syscallreturn.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "sim/faults.hh" 40#include "sim/host.hh" 41#include "sim/serialize.hh" 42#include "sim/byteswap.hh" 43 44// @todo: Figure out a more architecture independent way to obtain the ITB and 45// DTB pointers. 46class AlphaDTB; 47class AlphaITB; 48class BaseCPU; 49class EndQuiesceEvent; 50class Event; 51class TranslatingPort; 52class FunctionalPort; 53class VirtualPort; 54class Process; 55class System; 56namespace Kernel { 57 class Statistics; 58}; 59 60/** 61 * ThreadContext is the external interface to all thread state for 62 * anything outside of the CPU. It provides all accessor methods to 63 * state that might be needed by external objects, ranging from 64 * register values to things such as kernel stats. It is an abstract 65 * base class; the CPU can create its own ThreadContext by either 66 * deriving from it, or using the templated ProxyThreadContext. 67 * 68 * The ThreadContext is slightly different than the ExecContext. The 69 * ThreadContext provides access to an individual thread's state; an 70 * ExecContext provides ISA access to the CPU (meaning it is 71 * implicitly multithreaded on SMT systems). Additionally the 72 * ThreadState is an abstract class that exactly defines the 73 * interface; the ExecContext is a more implicit interface that must 74 * be implemented so that the ISA can access whatever state it needs. 75 */ 76class ThreadContext 77{ 78 protected: 79 typedef TheISA::RegFile RegFile; 80 typedef TheISA::MachInst MachInst; 81 typedef TheISA::IntReg IntReg; 82 typedef TheISA::FloatReg FloatReg; 83 typedef TheISA::FloatRegBits FloatRegBits; 84 typedef TheISA::MiscRegFile MiscRegFile; 85 typedef TheISA::MiscReg MiscReg; 86 public: 87 enum Status 88 { 89 /// Initialized but not running yet. All CPUs start in 90 /// this state, but most transition to Active on cycle 1. 91 /// In MP or SMT systems, non-primary contexts will stay 92 /// in this state until a thread is assigned to them. 93 Unallocated, 94 95 /// Running. Instructions should be executed only when 96 /// the context is in this state. 97 Active, 98 99 /// Temporarily inactive. Entered while waiting for 100 /// synchronization, etc. 101 Suspended, 102 103 /// Permanently shut down. Entered when target executes 104 /// m5exit pseudo-instruction. When all contexts enter 105 /// this state, the simulation will terminate. 106 Halted 107 }; 108 109 virtual ~ThreadContext() { }; 110 111 virtual BaseCPU *getCpuPtr() = 0; 112 113 virtual void setCpuId(int id) = 0; 114 115 virtual int readCpuId() = 0; 116 117#if FULL_SYSTEM 118 virtual System *getSystemPtr() = 0; 119 120 virtual AlphaITB *getITBPtr() = 0; 121 122 virtual AlphaDTB * getDTBPtr() = 0; 123 124 virtual Kernel::Statistics *getKernelStats() = 0; 125 126 virtual FunctionalPort *getPhysPort() = 0; 127 128 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 129 130 virtual void delVirtPort(VirtualPort *vp) = 0; 131#else 132 virtual TranslatingPort *getMemPort() = 0; 133 134 virtual Process *getProcessPtr() = 0; 135#endif 136 137 virtual Status status() const = 0; 138 139 virtual void setStatus(Status new_status) = 0; 140 141 /// Set the status to Active. Optional delay indicates number of 142 /// cycles to wait before beginning execution. 143 virtual void activate(int delay = 1) = 0; 144 145 /// Set the status to Suspended. 146 virtual void suspend() = 0; 147 148 /// Set the status to Unallocated. 149 virtual void deallocate(int delay = 0) = 0; 150 151 /// Set the status to Halted. 152 virtual void halt() = 0; 153 154#if FULL_SYSTEM 155 virtual void dumpFuncProfile() = 0; 156#endif 157 158 virtual void takeOverFrom(ThreadContext *old_context) = 0; 159 160 virtual void regStats(const std::string &name) = 0; 161 162 virtual void serialize(std::ostream &os) = 0; 163 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 164 165#if FULL_SYSTEM 166 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 167 168 // Not necessarily the best location for these... 169 // Having an extra function just to read these is obnoxious 170 virtual Tick readLastActivate() = 0; 171 virtual Tick readLastSuspend() = 0; 172 173 virtual void profileClear() = 0; 174 virtual void profileSample() = 0; 175#endif 176 177 virtual int getThreadNum() = 0; 178 179 // Also somewhat obnoxious. Really only used for the TLB fault. 180 // However, may be quite useful in SPARC. 181 virtual TheISA::MachInst getInst() = 0; 182 183 virtual void copyArchRegs(ThreadContext *tc) = 0; 184 185 virtual void clearArchRegs() = 0; 186 187 // 188 // New accessors for new decoder. 189 // 190 virtual uint64_t readIntReg(int reg_idx) = 0; 191 192 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 193 194 virtual FloatReg readFloatReg(int reg_idx) = 0; 195 196 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 197 198 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 199 200 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 201 202 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 203 204 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 205 206 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 207 208 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 209 210 virtual uint64_t readPC() = 0; 211 212 virtual void setPC(uint64_t val) = 0; 213 214 virtual uint64_t readNextPC() = 0; 215 216 virtual void setNextPC(uint64_t val) = 0; 217 218 virtual uint64_t readNextNPC() = 0; 219 220 virtual void setNextNPC(uint64_t val) = 0; 221 222 virtual MiscReg readMiscReg(int misc_reg) = 0; 223 224 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 225 226 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 227 228 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 229 230 // Also not necessarily the best location for these two. Hopefully will go 231 // away once we decide upon where st cond failures goes. 232 virtual unsigned readStCondFailures() = 0; 233 234 virtual void setStCondFailures(unsigned sc_failures) = 0; 235 236#if FULL_SYSTEM 237 virtual bool inPalMode() = 0; 238#endif 239 240 // Only really makes sense for old CPU model. Still could be useful though. 241 virtual bool misspeculating() = 0; 242 243#if !FULL_SYSTEM 244 virtual IntReg getSyscallArg(int i) = 0; 245 246 // used to shift args for indirect syscall 247 virtual void setSyscallArg(int i, IntReg val) = 0; 248 249 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 250 251 // Same with st cond failures. 252 virtual Counter readFuncExeInst() = 0; 253 254 // This function exits the thread context in the CPU and returns 255 // 1 if the CPU has no more active threads (meaning it's OK to exit); 256 // Used in syscall-emulation mode when a thread calls the exit syscall. 257 virtual int exit() { return 1; }; 258#endif 259 260 virtual void changeRegFileContext(TheISA::RegContextParam param, 261 TheISA::RegContextVal val) = 0; 262}; 263 264/** 265 * ProxyThreadContext class that provides a way to implement a 266 * ThreadContext without having to derive from it. ThreadContext is an 267 * abstract class, so anything that derives from it and uses its 268 * interface will pay the overhead of virtual function calls. This 269 * class is created to enable a user-defined Thread object to be used 270 * wherever ThreadContexts are used, without paying the overhead of 271 * virtual function calls when it is used by itself. See 272 * simple_thread.hh for an example of this. 273 */ 274template <class TC> 275class ProxyThreadContext : public ThreadContext 276{ 277 public: 278 ProxyThreadContext(TC *actual_tc) 279 { actualTC = actual_tc; } 280 281 private: 282 TC *actualTC; 283 284 public: 285 286 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 287 288 void setCpuId(int id) { actualTC->setCpuId(id); } 289 290 int readCpuId() { return actualTC->readCpuId(); } 291 292#if FULL_SYSTEM 293 System *getSystemPtr() { return actualTC->getSystemPtr(); } 294 295 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 296 297 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 298 299 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 300 301 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 302 303 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 304 305 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 306#else 307 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 308 309 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 310#endif 311 312 Status status() const { return actualTC->status(); } 313 314 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 315 316 /// Set the status to Active. Optional delay indicates number of 317 /// cycles to wait before beginning execution. 318 void activate(int delay = 1) { actualTC->activate(delay); } 319 320 /// Set the status to Suspended. 321 void suspend() { actualTC->suspend(); } 322 323 /// Set the status to Unallocated. 324 void deallocate(int delay = 0) { actualTC->deallocate(); } 325 326 /// Set the status to Halted. 327 void halt() { actualTC->halt(); } 328 329#if FULL_SYSTEM 330 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 331#endif 332 333 void takeOverFrom(ThreadContext *oldContext) 334 { actualTC->takeOverFrom(oldContext); } 335 336 void regStats(const std::string &name) { actualTC->regStats(name); } 337 338 void serialize(std::ostream &os) { actualTC->serialize(os); } 339 void unserialize(Checkpoint *cp, const std::string §ion) 340 { actualTC->unserialize(cp, section); } 341 342#if FULL_SYSTEM 343 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 344 345 Tick readLastActivate() { return actualTC->readLastActivate(); } 346 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 347 348 void profileClear() { return actualTC->profileClear(); } 349 void profileSample() { return actualTC->profileSample(); } 350#endif 351 352 int getThreadNum() { return actualTC->getThreadNum(); } 353 354 // @todo: Do I need this? 355 MachInst getInst() { return actualTC->getInst(); } 356 357 // @todo: Do I need this? 358 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 359 360 void clearArchRegs() { actualTC->clearArchRegs(); } 361 362 // 363 // New accessors for new decoder. 364 // 365 uint64_t readIntReg(int reg_idx) 366 { return actualTC->readIntReg(reg_idx); } 367 368 FloatReg readFloatReg(int reg_idx, int width) 369 { return actualTC->readFloatReg(reg_idx, width); } 370 371 FloatReg readFloatReg(int reg_idx) 372 { return actualTC->readFloatReg(reg_idx); } 373 374 FloatRegBits readFloatRegBits(int reg_idx, int width) 375 { return actualTC->readFloatRegBits(reg_idx, width); } 376 377 FloatRegBits readFloatRegBits(int reg_idx) 378 { return actualTC->readFloatRegBits(reg_idx); } 379 380 void setIntReg(int reg_idx, uint64_t val) 381 { actualTC->setIntReg(reg_idx, val); } 382 383 void setFloatReg(int reg_idx, FloatReg val, int width) 384 { actualTC->setFloatReg(reg_idx, val, width); } 385 386 void setFloatReg(int reg_idx, FloatReg val) 387 { actualTC->setFloatReg(reg_idx, val); } 388 389 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 390 { actualTC->setFloatRegBits(reg_idx, val, width); } 391 392 void setFloatRegBits(int reg_idx, FloatRegBits val) 393 { actualTC->setFloatRegBits(reg_idx, val); } 394 395 uint64_t readPC() { return actualTC->readPC(); } 396 397 void setPC(uint64_t val) { actualTC->setPC(val); } 398 399 uint64_t readNextPC() { return actualTC->readNextPC(); } 400 401 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 402 403 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 404 405 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 406 407 MiscReg readMiscReg(int misc_reg) 408 { return actualTC->readMiscReg(misc_reg); } 409 410 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 411 { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 412 413 Fault setMiscReg(int misc_reg, const MiscReg &val) 414 { return actualTC->setMiscReg(misc_reg, val); } 415 416 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 417 { return actualTC->setMiscRegWithEffect(misc_reg, val); } 418 419 unsigned readStCondFailures() 420 { return actualTC->readStCondFailures(); } 421 422 void setStCondFailures(unsigned sc_failures) 423 { actualTC->setStCondFailures(sc_failures); } 424#if FULL_SYSTEM 425 bool inPalMode() { return actualTC->inPalMode(); } 426#endif 427 428 // @todo: Fix this! 429 bool misspeculating() { return actualTC->misspeculating(); } 430 431#if !FULL_SYSTEM 432 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 433 434 // used to shift args for indirect syscall 435 void setSyscallArg(int i, IntReg val) 436 { actualTC->setSyscallArg(i, val); } 437 438 void setSyscallReturn(SyscallReturn return_value) 439 { actualTC->setSyscallReturn(return_value); } 440 441 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 442#endif 443 444 void changeRegFileContext(TheISA::RegContextParam param, 445 TheISA::RegContextVal val) 446 { 447 actualTC->changeRegFileContext(param, val); 448 } 449}; 450 451#endif 452