thread_context.hh revision 2036
111731Sjason@lowepower.com/* 211731Sjason@lowepower.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 311731Sjason@lowepower.com * All rights reserved. 411731Sjason@lowepower.com * 511731Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 611731Sjason@lowepower.com * modification, are permitted provided that the following conditions are 711731Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 811731Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 911731Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 1011731Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 1111731Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 1211731Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 1311731Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 1411731Sjason@lowepower.com * this software without specific prior written permission. 1511731Sjason@lowepower.com * 1611731Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711731Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811731Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911731Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011731Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111731Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211731Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311731Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411731Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511731Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611731Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711731Sjason@lowepower.com */ 2811731Sjason@lowepower.com 2911731Sjason@lowepower.com#ifndef __CPU_EXEC_CONTEXT_HH__ 3011731Sjason@lowepower.com#define __CPU_EXEC_CONTEXT_HH__ 3111731Sjason@lowepower.com 3211731Sjason@lowepower.com#include "config/full_system.hh" 3311731Sjason@lowepower.com#include "mem/functional/functional.hh" 3411731Sjason@lowepower.com#include "mem/mem_req.hh" 3511731Sjason@lowepower.com#include "sim/host.hh" 3611731Sjason@lowepower.com#include "sim/serialize.hh" 3711731Sjason@lowepower.com#include "sim/byteswap.hh" 3811731Sjason@lowepower.com 3911731Sjason@lowepower.com// forward declaration: see functional_memory.hh 4011731Sjason@lowepower.comclass FunctionalMemory; 4111731Sjason@lowepower.comclass PhysicalMemory; 4211731Sjason@lowepower.comclass BaseCPU; 4311731Sjason@lowepower.com 4411731Sjason@lowepower.com#if FULL_SYSTEM 4511731Sjason@lowepower.com 4611731Sjason@lowepower.com#include "sim/system.hh" 4711731Sjason@lowepower.com#include "targetarch/alpha_memory.hh" 4811731Sjason@lowepower.com 4911731Sjason@lowepower.comclass FunctionProfile; 5011731Sjason@lowepower.comclass ProfileNode; 5111731Sjason@lowepower.comclass MemoryController; 5211731Sjason@lowepower.comnamespace Kernel { class Binning; class Statistics; } 5311731Sjason@lowepower.com 5411731Sjason@lowepower.com#else // !FULL_SYSTEM 5511731Sjason@lowepower.com 5611731Sjason@lowepower.com#include "sim/process.hh" 5711731Sjason@lowepower.com 5811731Sjason@lowepower.com#endif // FULL_SYSTEM 5911731Sjason@lowepower.com 6011731Sjason@lowepower.com// 6111731Sjason@lowepower.com// The ExecContext object represents a functional context for 6211731Sjason@lowepower.com// instruction execution. It incorporates everything required for 6311731Sjason@lowepower.com// architecture-level functional simulation of a single thread. 6411731Sjason@lowepower.com// 6511731Sjason@lowepower.com 6611731Sjason@lowepower.comclass ExecContext 6711731Sjason@lowepower.com{ 6811731Sjason@lowepower.com public: 6911731Sjason@lowepower.com enum Status 7011731Sjason@lowepower.com { 7111731Sjason@lowepower.com /// Initialized but not running yet. All CPUs start in 7211731Sjason@lowepower.com /// this state, but most transition to Active on cycle 1. 7311731Sjason@lowepower.com /// In MP or SMT systems, non-primary contexts will stay 7411731Sjason@lowepower.com /// in this state until a thread is assigned to them. 7511731Sjason@lowepower.com Unallocated, 7611731Sjason@lowepower.com 7711731Sjason@lowepower.com /// Running. Instructions should be executed only when 7811731Sjason@lowepower.com /// the context is in this state. 7911731Sjason@lowepower.com Active, 8011731Sjason@lowepower.com 8111731Sjason@lowepower.com /// Temporarily inactive. Entered while waiting for 8211731Sjason@lowepower.com /// synchronization, etc. 8311731Sjason@lowepower.com Suspended, 8411731Sjason@lowepower.com 8511731Sjason@lowepower.com /// Permanently shut down. Entered when target executes 8611731Sjason@lowepower.com /// m5exit pseudo-instruction. When all contexts enter 8711731Sjason@lowepower.com /// this state, the simulation will terminate. 8812137Sar4jc@virginia.edu Halted 8911731Sjason@lowepower.com }; 9011731Sjason@lowepower.com 9112137Sar4jc@virginia.edu private: 9211731Sjason@lowepower.com Status _status; 9311731Sjason@lowepower.com 9411731Sjason@lowepower.com public: 9511731Sjason@lowepower.com Status status() const { return _status; } 9611731Sjason@lowepower.com 9711731Sjason@lowepower.com /// Set the status to Active. Optional delay indicates number of 9811731Sjason@lowepower.com /// cycles to wait before beginning execution. 9911731Sjason@lowepower.com void activate(int delay = 1); 10011731Sjason@lowepower.com 10111731Sjason@lowepower.com /// Set the status to Suspended. 10211731Sjason@lowepower.com void suspend(); 10311731Sjason@lowepower.com 10411731Sjason@lowepower.com /// Set the status to Unallocated. 10511731Sjason@lowepower.com void deallocate(); 10611731Sjason@lowepower.com 10711731Sjason@lowepower.com /// Set the status to Halted. 10811731Sjason@lowepower.com void halt(); 10911731Sjason@lowepower.com 11011731Sjason@lowepower.com public: 11111731Sjason@lowepower.com RegFile regs; // correct-path register context 11211731Sjason@lowepower.com 11311731Sjason@lowepower.com // pointer to CPU associated with this context 11411731Sjason@lowepower.com BaseCPU *cpu; 11511731Sjason@lowepower.com 11611731Sjason@lowepower.com // Current instruction 11711731Sjason@lowepower.com MachInst inst; 11811731Sjason@lowepower.com 11911731Sjason@lowepower.com // Index of hardware thread context on the CPU that this represents. 12011731Sjason@lowepower.com int thread_num; 12111731Sjason@lowepower.com 12211731Sjason@lowepower.com // ID of this context w.r.t. the System or Process object to which 12311731Sjason@lowepower.com // it belongs. For full-system mode, this is the system CPU ID. 12411731Sjason@lowepower.com int cpu_id; 12511731Sjason@lowepower.com 12611731Sjason@lowepower.com#if FULL_SYSTEM 12712137Sar4jc@virginia.edu FunctionalMemory *mem; 12811731Sjason@lowepower.com AlphaITB *itb; 12911731Sjason@lowepower.com AlphaDTB *dtb; 13011731Sjason@lowepower.com System *system; 13111731Sjason@lowepower.com 13211731Sjason@lowepower.com // the following two fields are redundant, since we can always 13311731Sjason@lowepower.com // look them up through the system pointer, but we'll leave them 13411731Sjason@lowepower.com // here for now for convenience 13511731Sjason@lowepower.com MemoryController *memctrl; 13612137Sar4jc@virginia.edu PhysicalMemory *physmem; 13711731Sjason@lowepower.com 13811731Sjason@lowepower.com Kernel::Binning *kernelBinning; 13911731Sjason@lowepower.com Kernel::Statistics *kernelStats; 14012137Sar4jc@virginia.edu bool bin; 14111731Sjason@lowepower.com bool fnbin; 14212137Sar4jc@virginia.edu 14311731Sjason@lowepower.com FunctionProfile *profile; 14412137Sar4jc@virginia.edu ProfileNode *profileNode; 14511731Sjason@lowepower.com Addr profilePC; 14611731Sjason@lowepower.com void dumpFuncProfile(); 14711731Sjason@lowepower.com 14811731Sjason@lowepower.com#else 14911731Sjason@lowepower.com Process *process; 15011731Sjason@lowepower.com 15111731Sjason@lowepower.com FunctionalMemory *mem; // functional storage for process address space 15211731Sjason@lowepower.com 15311731Sjason@lowepower.com // Address space ID. Note that this is used for TIMING cache 15411731Sjason@lowepower.com // simulation only; all functional memory accesses should use 15511731Sjason@lowepower.com // one of the FunctionalMemory pointers above. 15611731Sjason@lowepower.com short asid; 15711731Sjason@lowepower.com 15811731Sjason@lowepower.com#endif 15911731Sjason@lowepower.com 16011731Sjason@lowepower.com /** 16111731Sjason@lowepower.com * Temporary storage to pass the source address from copy_load to 16211731Sjason@lowepower.com * copy_store. 16311731Sjason@lowepower.com * @todo Remove this temporary when we have a better way to do it. 16411731Sjason@lowepower.com */ 16511731Sjason@lowepower.com Addr copySrcAddr; 16611731Sjason@lowepower.com /** 16711731Sjason@lowepower.com * Temp storage for the physical source address of a copy. 16811731Sjason@lowepower.com * @todo Remove this temporary when we have a better way to do it. 16911731Sjason@lowepower.com */ 17011731Sjason@lowepower.com Addr copySrcPhysAddr; 17111731Sjason@lowepower.com 17211731Sjason@lowepower.com 17311731Sjason@lowepower.com /* 17411731Sjason@lowepower.com * number of executed instructions, for matching with syscall trace 17511731Sjason@lowepower.com * points in EIO files. 17611731Sjason@lowepower.com */ 17711731Sjason@lowepower.com Counter func_exe_inst; 17811731Sjason@lowepower.com 17911731Sjason@lowepower.com // 18011731Sjason@lowepower.com // Count failed store conditionals so we can warn of apparent 18111731Sjason@lowepower.com // application deadlock situations. 18211731Sjason@lowepower.com unsigned storeCondFailures; 18311731Sjason@lowepower.com 18411731Sjason@lowepower.com // constructor: initialize context from given process structure 18511731Sjason@lowepower.com#if FULL_SYSTEM 18611731Sjason@lowepower.com ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 18711731Sjason@lowepower.com AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 18811731Sjason@lowepower.com#else 18911731Sjason@lowepower.com ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 19011731Sjason@lowepower.com ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 19111731Sjason@lowepower.com int _asid); 19211731Sjason@lowepower.com#endif 19311731Sjason@lowepower.com virtual ~ExecContext(); 19411731Sjason@lowepower.com 19511731Sjason@lowepower.com virtual void takeOverFrom(ExecContext *oldContext); 19611731Sjason@lowepower.com 19711731Sjason@lowepower.com void regStats(const std::string &name); 19811731Sjason@lowepower.com 19911731Sjason@lowepower.com void serialize(std::ostream &os); 20011731Sjason@lowepower.com void unserialize(Checkpoint *cp, const std::string §ion); 20111731Sjason@lowepower.com 20211731Sjason@lowepower.com#if FULL_SYSTEM 20311731Sjason@lowepower.com bool validInstAddr(Addr addr) { return true; } 20411731Sjason@lowepower.com bool validDataAddr(Addr addr) { return true; } 20511731Sjason@lowepower.com int getInstAsid() { return regs.instAsid(); } 20611731Sjason@lowepower.com int getDataAsid() { return regs.dataAsid(); } 20711731Sjason@lowepower.com 20811731Sjason@lowepower.com Fault translateInstReq(MemReqPtr &req) 20911731Sjason@lowepower.com { 21011731Sjason@lowepower.com return itb->translate(req); 21111731Sjason@lowepower.com } 21211731Sjason@lowepower.com 21311731Sjason@lowepower.com Fault translateDataReadReq(MemReqPtr &req) 21411731Sjason@lowepower.com { 21511731Sjason@lowepower.com return dtb->translate(req, false); 21611731Sjason@lowepower.com } 21711731Sjason@lowepower.com 21811731Sjason@lowepower.com Fault translateDataWriteReq(MemReqPtr &req) 21911731Sjason@lowepower.com { 22011731Sjason@lowepower.com return dtb->translate(req, true); 22111731Sjason@lowepower.com } 22211731Sjason@lowepower.com 22311731Sjason@lowepower.com#else 22411731Sjason@lowepower.com bool validInstAddr(Addr addr) 22511731Sjason@lowepower.com { return process->validInstAddr(addr); } 22611731Sjason@lowepower.com 22711731Sjason@lowepower.com bool validDataAddr(Addr addr) 22811731Sjason@lowepower.com { return process->validDataAddr(addr); } 22911731Sjason@lowepower.com 23011731Sjason@lowepower.com int getInstAsid() { return asid; } 23111731Sjason@lowepower.com int getDataAsid() { return asid; } 23211731Sjason@lowepower.com 23311731Sjason@lowepower.com Fault dummyTranslation(MemReqPtr &req) 23411731Sjason@lowepower.com { 23511731Sjason@lowepower.com#if 0 23611731Sjason@lowepower.com assert((req->vaddr >> 48 & 0xffff) == 0); 23711731Sjason@lowepower.com#endif 23811731Sjason@lowepower.com 23911731Sjason@lowepower.com // put the asid in the upper 16 bits of the paddr 24011731Sjason@lowepower.com req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 24111731Sjason@lowepower.com req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 24211731Sjason@lowepower.com return No_Fault; 24311731Sjason@lowepower.com } 24411731Sjason@lowepower.com Fault translateInstReq(MemReqPtr &req) 24511731Sjason@lowepower.com { 24611731Sjason@lowepower.com return dummyTranslation(req); 24711731Sjason@lowepower.com } 24811731Sjason@lowepower.com Fault translateDataReadReq(MemReqPtr &req) 24911731Sjason@lowepower.com { 25011731Sjason@lowepower.com return dummyTranslation(req); 25111731Sjason@lowepower.com } 25211731Sjason@lowepower.com Fault translateDataWriteReq(MemReqPtr &req) 25311731Sjason@lowepower.com { 25411731Sjason@lowepower.com return dummyTranslation(req); 25511731Sjason@lowepower.com } 25611731Sjason@lowepower.com 25711731Sjason@lowepower.com#endif 25811731Sjason@lowepower.com 25911731Sjason@lowepower.com template <class T> 26011731Sjason@lowepower.com Fault read(MemReqPtr &req, T &data) 26111731Sjason@lowepower.com { 26211731Sjason@lowepower.com#if FULL_SYSTEM && defined(TARGET_ALPHA) 26311731Sjason@lowepower.com if (req->flags & LOCKED) { 26411731Sjason@lowepower.com MiscRegFile *cregs = &req->xc->regs.miscRegs; 26511731Sjason@lowepower.com cregs->lock_addr = req->paddr; 26611731Sjason@lowepower.com cregs->lock_flag = true; 26711731Sjason@lowepower.com } 26811731Sjason@lowepower.com#endif 26911731Sjason@lowepower.com 27011731Sjason@lowepower.com Fault error; 27111731Sjason@lowepower.com error = mem->read(req, data); 27212137Sar4jc@virginia.edu data = LittleEndianGuest::gtoh(data); 27311731Sjason@lowepower.com return error; 27411731Sjason@lowepower.com } 27511731Sjason@lowepower.com 27611731Sjason@lowepower.com template <class T> 27711731Sjason@lowepower.com Fault write(MemReqPtr &req, T &data) 27811731Sjason@lowepower.com { 27911731Sjason@lowepower.com#if FULL_SYSTEM && defined(TARGET_ALPHA) 28011731Sjason@lowepower.com 28111731Sjason@lowepower.com MiscRegFile *cregs; 28211731Sjason@lowepower.com 28311731Sjason@lowepower.com // If this is a store conditional, act appropriately 28411731Sjason@lowepower.com if (req->flags & LOCKED) { 28511731Sjason@lowepower.com cregs = &req->xc->regs.miscRegs; 28611731Sjason@lowepower.com 28711731Sjason@lowepower.com if (req->flags & UNCACHEABLE) { 28811731Sjason@lowepower.com // Don't update result register (see stq_c in isa_desc) 28911731Sjason@lowepower.com req->result = 2; 29011731Sjason@lowepower.com req->xc->storeCondFailures = 0;//Needed? [RGD] 29111731Sjason@lowepower.com } else { 29211731Sjason@lowepower.com req->result = cregs->lock_flag; 29311731Sjason@lowepower.com if (!cregs->lock_flag || 29411731Sjason@lowepower.com ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 29512137Sar4jc@virginia.edu cregs->lock_flag = false; 29611731Sjason@lowepower.com if (((++req->xc->storeCondFailures) % 100000) == 0) { 29711731Sjason@lowepower.com std::cerr << "Warning: " 29811731Sjason@lowepower.com << req->xc->storeCondFailures 29911731Sjason@lowepower.com << " consecutive store conditional failures " 30011731Sjason@lowepower.com << "on cpu " << req->xc->cpu_id 30112137Sar4jc@virginia.edu << std::endl; 30211731Sjason@lowepower.com } 30311731Sjason@lowepower.com return No_Fault; 30411731Sjason@lowepower.com } 30511731Sjason@lowepower.com else req->xc->storeCondFailures = 0; 30611731Sjason@lowepower.com } 30711731Sjason@lowepower.com } 30811731Sjason@lowepower.com 30911731Sjason@lowepower.com // Need to clear any locked flags on other proccessors for 31011731Sjason@lowepower.com // this address. Only do this for succsful Store Conditionals 31111731Sjason@lowepower.com // and all other stores (WH64?). Unsuccessful Store 31211731Sjason@lowepower.com // Conditionals would have returned above, and wouldn't fall 31311731Sjason@lowepower.com // through. 31411731Sjason@lowepower.com for (int i = 0; i < system->execContexts.size(); i++){ 31511731Sjason@lowepower.com cregs = &system->execContexts[i]->regs.miscRegs; 31611731Sjason@lowepower.com if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 31711731Sjason@lowepower.com cregs->lock_flag = false; 31811731Sjason@lowepower.com } 31911731Sjason@lowepower.com } 32011731Sjason@lowepower.com 32111731Sjason@lowepower.com#endif 32211731Sjason@lowepower.com return mem->write(req, (T)LittleEndianGuest::htog(data)); 32311731Sjason@lowepower.com } 32411731Sjason@lowepower.com 32511731Sjason@lowepower.com virtual bool misspeculating(); 32611731Sjason@lowepower.com 32711731Sjason@lowepower.com 32811731Sjason@lowepower.com MachInst getInst() { return inst; } 32911731Sjason@lowepower.com 33011731Sjason@lowepower.com void setInst(MachInst new_inst) 33111731Sjason@lowepower.com { 33211731Sjason@lowepower.com inst = new_inst; 33311731Sjason@lowepower.com } 33411731Sjason@lowepower.com 33511731Sjason@lowepower.com Fault instRead(MemReqPtr &req) 33611731Sjason@lowepower.com { 33711731Sjason@lowepower.com return mem->read(req, inst); 33811731Sjason@lowepower.com } 33911731Sjason@lowepower.com 34011731Sjason@lowepower.com // 34111731Sjason@lowepower.com // New accessors for new decoder. 34211731Sjason@lowepower.com // 34311731Sjason@lowepower.com uint64_t readIntReg(int reg_idx) 34411731Sjason@lowepower.com { 34511731Sjason@lowepower.com return regs.intRegFile[reg_idx]; 34611731Sjason@lowepower.com } 34711731Sjason@lowepower.com 34811731Sjason@lowepower.com float readFloatRegSingle(int reg_idx) 34911731Sjason@lowepower.com { 35011731Sjason@lowepower.com return (float)regs.floatRegFile.d[reg_idx]; 35111731Sjason@lowepower.com } 35211731Sjason@lowepower.com 35311731Sjason@lowepower.com double readFloatRegDouble(int reg_idx) 35412137Sar4jc@virginia.edu { 35511731Sjason@lowepower.com return regs.floatRegFile.d[reg_idx]; 35611731Sjason@lowepower.com } 35711731Sjason@lowepower.com 35811731Sjason@lowepower.com uint64_t readFloatRegInt(int reg_idx) 35911731Sjason@lowepower.com { 36011731Sjason@lowepower.com return regs.floatRegFile.q[reg_idx]; 36111731Sjason@lowepower.com } 36211731Sjason@lowepower.com 36311731Sjason@lowepower.com void setIntReg(int reg_idx, uint64_t val) 36411731Sjason@lowepower.com { 36511731Sjason@lowepower.com regs.intRegFile[reg_idx] = val; 36611731Sjason@lowepower.com } 36711731Sjason@lowepower.com 36811731Sjason@lowepower.com void setFloatRegSingle(int reg_idx, float val) 36911731Sjason@lowepower.com { 37011731Sjason@lowepower.com regs.floatRegFile.d[reg_idx] = (double)val; 37111731Sjason@lowepower.com } 37211731Sjason@lowepower.com 37311731Sjason@lowepower.com void setFloatRegDouble(int reg_idx, double val) 37411731Sjason@lowepower.com { 37511731Sjason@lowepower.com regs.floatRegFile.d[reg_idx] = val; 37611731Sjason@lowepower.com } 37711731Sjason@lowepower.com 37811731Sjason@lowepower.com void setFloatRegInt(int reg_idx, uint64_t val) 37911731Sjason@lowepower.com { 38011731Sjason@lowepower.com regs.floatRegFile.q[reg_idx] = val; 38111731Sjason@lowepower.com } 38211731Sjason@lowepower.com 38311731Sjason@lowepower.com uint64_t readPC() 38411731Sjason@lowepower.com { 38511731Sjason@lowepower.com return regs.pc; 38611731Sjason@lowepower.com } 38711731Sjason@lowepower.com 38811731Sjason@lowepower.com void setNextPC(uint64_t val) 38911731Sjason@lowepower.com { 39011731Sjason@lowepower.com regs.npc = val; 39111731Sjason@lowepower.com } 39211731Sjason@lowepower.com 39311731Sjason@lowepower.com uint64_t readUniq() 39411731Sjason@lowepower.com { 39511731Sjason@lowepower.com return regs.miscRegs.uniq; 39611731Sjason@lowepower.com } 39711731Sjason@lowepower.com 39811731Sjason@lowepower.com void setUniq(uint64_t val) 39911731Sjason@lowepower.com { 40011731Sjason@lowepower.com regs.miscRegs.uniq = val; 40111731Sjason@lowepower.com } 40211731Sjason@lowepower.com 40311731Sjason@lowepower.com uint64_t readFpcr() 40411731Sjason@lowepower.com { 40511731Sjason@lowepower.com return regs.miscRegs.fpcr; 40611731Sjason@lowepower.com } 40711731Sjason@lowepower.com 40811731Sjason@lowepower.com void setFpcr(uint64_t val) 40911731Sjason@lowepower.com { 41011731Sjason@lowepower.com regs.miscRegs.fpcr = val; 41111731Sjason@lowepower.com } 41211731Sjason@lowepower.com 41311731Sjason@lowepower.com#if FULL_SYSTEM 41411731Sjason@lowepower.com uint64_t readIpr(int idx, Fault &fault); 41511731Sjason@lowepower.com Fault setIpr(int idx, uint64_t val); 41611731Sjason@lowepower.com int readIntrFlag() { return regs.intrflag; } 41711731Sjason@lowepower.com void setIntrFlag(int val) { regs.intrflag = val; } 41811731Sjason@lowepower.com Fault hwrei(); 41911731Sjason@lowepower.com bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 42011731Sjason@lowepower.com void ev5_trap(Fault fault); 42111731Sjason@lowepower.com bool simPalCheck(int palFunc); 42211731Sjason@lowepower.com#endif 42311731Sjason@lowepower.com 42411731Sjason@lowepower.com /** Meant to be more generic trap function to be 42511731Sjason@lowepower.com * called when an instruction faults. 42611731Sjason@lowepower.com * @param fault The fault generated by executing the instruction. 42711731Sjason@lowepower.com * @todo How to do this properly so it's dependent upon ISA only? 42811731Sjason@lowepower.com */ 42911731Sjason@lowepower.com 43011731Sjason@lowepower.com void trap(Fault fault); 43111731Sjason@lowepower.com 43211731Sjason@lowepower.com#if !FULL_SYSTEM 43311731Sjason@lowepower.com IntReg getSyscallArg(int i) 43411731Sjason@lowepower.com { 43511731Sjason@lowepower.com return regs.intRegFile[ArgumentReg0 + i]; 43611731Sjason@lowepower.com } 43711731Sjason@lowepower.com 43811731Sjason@lowepower.com // used to shift args for indirect syscall 43911731Sjason@lowepower.com void setSyscallArg(int i, IntReg val) 44011731Sjason@lowepower.com { 44111731Sjason@lowepower.com regs.intRegFile[ArgumentReg0 + i] = val; 44211731Sjason@lowepower.com } 44311731Sjason@lowepower.com 44411731Sjason@lowepower.com void setSyscallReturn(SyscallReturn return_value) 44511731Sjason@lowepower.com { 44611731Sjason@lowepower.com // check for error condition. Alpha syscall convention is to 44711731Sjason@lowepower.com // indicate success/failure in reg a3 (r19) and put the 44811731Sjason@lowepower.com // return value itself in the standard return value reg (v0). 44911731Sjason@lowepower.com const int RegA3 = 19; // only place this is used 45011731Sjason@lowepower.com if (return_value.successful()) { 45111731Sjason@lowepower.com // no error 45211731Sjason@lowepower.com regs.intRegFile[RegA3] = 0; 45311731Sjason@lowepower.com regs.intRegFile[ReturnValueReg] = return_value.value(); 45411731Sjason@lowepower.com } else { 45511731Sjason@lowepower.com // got an error, return details 45611731Sjason@lowepower.com regs.intRegFile[RegA3] = (IntReg) -1; 45711731Sjason@lowepower.com regs.intRegFile[ReturnValueReg] = -return_value.value(); 45811731Sjason@lowepower.com } 45911731Sjason@lowepower.com } 46011731Sjason@lowepower.com 46111731Sjason@lowepower.com void syscall() 46211731Sjason@lowepower.com { 46311731Sjason@lowepower.com process->syscall(this); 46411731Sjason@lowepower.com } 46511731Sjason@lowepower.com#endif 46611731Sjason@lowepower.com}; 46711731Sjason@lowepower.com 46811731Sjason@lowepower.com 46911731Sjason@lowepower.com// for non-speculative execution context, spec_mode is always false 47011731Sjason@lowepower.cominline bool 47111731Sjason@lowepower.comExecContext::misspeculating() 47211731Sjason@lowepower.com{ 47311731Sjason@lowepower.com return false; 47411731Sjason@lowepower.com} 47511731Sjason@lowepower.com 47611731Sjason@lowepower.com#endif // __CPU_EXEC_CONTEXT_HH__ 47711731Sjason@lowepower.com