thread_context.hh revision 2036
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/functional/functional.hh" 34#include "mem/mem_req.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// forward declaration: see functional_memory.hh 40class FunctionalMemory; 41class PhysicalMemory; 42class BaseCPU; 43 44#if FULL_SYSTEM 45 46#include "sim/system.hh" 47#include "targetarch/alpha_memory.hh" 48 49class FunctionProfile; 50class ProfileNode; 51class MemoryController; 52namespace Kernel { class Binning; class Statistics; } 53 54#else // !FULL_SYSTEM 55 56#include "sim/process.hh" 57 58#endif // FULL_SYSTEM 59 60// 61// The ExecContext object represents a functional context for 62// instruction execution. It incorporates everything required for 63// architecture-level functional simulation of a single thread. 64// 65 66class ExecContext 67{ 68 public: 69 enum Status 70 { 71 /// Initialized but not running yet. All CPUs start in 72 /// this state, but most transition to Active on cycle 1. 73 /// In MP or SMT systems, non-primary contexts will stay 74 /// in this state until a thread is assigned to them. 75 Unallocated, 76 77 /// Running. Instructions should be executed only when 78 /// the context is in this state. 79 Active, 80 81 /// Temporarily inactive. Entered while waiting for 82 /// synchronization, etc. 83 Suspended, 84 85 /// Permanently shut down. Entered when target executes 86 /// m5exit pseudo-instruction. When all contexts enter 87 /// this state, the simulation will terminate. 88 Halted 89 }; 90 91 private: 92 Status _status; 93 94 public: 95 Status status() const { return _status; } 96 97 /// Set the status to Active. Optional delay indicates number of 98 /// cycles to wait before beginning execution. 99 void activate(int delay = 1); 100 101 /// Set the status to Suspended. 102 void suspend(); 103 104 /// Set the status to Unallocated. 105 void deallocate(); 106 107 /// Set the status to Halted. 108 void halt(); 109 110 public: 111 RegFile regs; // correct-path register context 112 113 // pointer to CPU associated with this context 114 BaseCPU *cpu; 115 116 // Current instruction 117 MachInst inst; 118 119 // Index of hardware thread context on the CPU that this represents. 120 int thread_num; 121 122 // ID of this context w.r.t. the System or Process object to which 123 // it belongs. For full-system mode, this is the system CPU ID. 124 int cpu_id; 125 126#if FULL_SYSTEM 127 FunctionalMemory *mem; 128 AlphaITB *itb; 129 AlphaDTB *dtb; 130 System *system; 131 132 // the following two fields are redundant, since we can always 133 // look them up through the system pointer, but we'll leave them 134 // here for now for convenience 135 MemoryController *memctrl; 136 PhysicalMemory *physmem; 137 138 Kernel::Binning *kernelBinning; 139 Kernel::Statistics *kernelStats; 140 bool bin; 141 bool fnbin; 142 143 FunctionProfile *profile; 144 ProfileNode *profileNode; 145 Addr profilePC; 146 void dumpFuncProfile(); 147 148#else 149 Process *process; 150 151 FunctionalMemory *mem; // functional storage for process address space 152 153 // Address space ID. Note that this is used for TIMING cache 154 // simulation only; all functional memory accesses should use 155 // one of the FunctionalMemory pointers above. 156 short asid; 157 158#endif 159 160 /** 161 * Temporary storage to pass the source address from copy_load to 162 * copy_store. 163 * @todo Remove this temporary when we have a better way to do it. 164 */ 165 Addr copySrcAddr; 166 /** 167 * Temp storage for the physical source address of a copy. 168 * @todo Remove this temporary when we have a better way to do it. 169 */ 170 Addr copySrcPhysAddr; 171 172 173 /* 174 * number of executed instructions, for matching with syscall trace 175 * points in EIO files. 176 */ 177 Counter func_exe_inst; 178 179 // 180 // Count failed store conditionals so we can warn of apparent 181 // application deadlock situations. 182 unsigned storeCondFailures; 183 184 // constructor: initialize context from given process structure 185#if FULL_SYSTEM 186 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 187 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 188#else 189 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 190 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 191 int _asid); 192#endif 193 virtual ~ExecContext(); 194 195 virtual void takeOverFrom(ExecContext *oldContext); 196 197 void regStats(const std::string &name); 198 199 void serialize(std::ostream &os); 200 void unserialize(Checkpoint *cp, const std::string §ion); 201 202#if FULL_SYSTEM 203 bool validInstAddr(Addr addr) { return true; } 204 bool validDataAddr(Addr addr) { return true; } 205 int getInstAsid() { return regs.instAsid(); } 206 int getDataAsid() { return regs.dataAsid(); } 207 208 Fault translateInstReq(MemReqPtr &req) 209 { 210 return itb->translate(req); 211 } 212 213 Fault translateDataReadReq(MemReqPtr &req) 214 { 215 return dtb->translate(req, false); 216 } 217 218 Fault translateDataWriteReq(MemReqPtr &req) 219 { 220 return dtb->translate(req, true); 221 } 222 223#else 224 bool validInstAddr(Addr addr) 225 { return process->validInstAddr(addr); } 226 227 bool validDataAddr(Addr addr) 228 { return process->validDataAddr(addr); } 229 230 int getInstAsid() { return asid; } 231 int getDataAsid() { return asid; } 232 233 Fault dummyTranslation(MemReqPtr &req) 234 { 235#if 0 236 assert((req->vaddr >> 48 & 0xffff) == 0); 237#endif 238 239 // put the asid in the upper 16 bits of the paddr 240 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 241 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 242 return No_Fault; 243 } 244 Fault translateInstReq(MemReqPtr &req) 245 { 246 return dummyTranslation(req); 247 } 248 Fault translateDataReadReq(MemReqPtr &req) 249 { 250 return dummyTranslation(req); 251 } 252 Fault translateDataWriteReq(MemReqPtr &req) 253 { 254 return dummyTranslation(req); 255 } 256 257#endif 258 259 template <class T> 260 Fault read(MemReqPtr &req, T &data) 261 { 262#if FULL_SYSTEM && defined(TARGET_ALPHA) 263 if (req->flags & LOCKED) { 264 MiscRegFile *cregs = &req->xc->regs.miscRegs; 265 cregs->lock_addr = req->paddr; 266 cregs->lock_flag = true; 267 } 268#endif 269 270 Fault error; 271 error = mem->read(req, data); 272 data = LittleEndianGuest::gtoh(data); 273 return error; 274 } 275 276 template <class T> 277 Fault write(MemReqPtr &req, T &data) 278 { 279#if FULL_SYSTEM && defined(TARGET_ALPHA) 280 281 MiscRegFile *cregs; 282 283 // If this is a store conditional, act appropriately 284 if (req->flags & LOCKED) { 285 cregs = &req->xc->regs.miscRegs; 286 287 if (req->flags & UNCACHEABLE) { 288 // Don't update result register (see stq_c in isa_desc) 289 req->result = 2; 290 req->xc->storeCondFailures = 0;//Needed? [RGD] 291 } else { 292 req->result = cregs->lock_flag; 293 if (!cregs->lock_flag || 294 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 295 cregs->lock_flag = false; 296 if (((++req->xc->storeCondFailures) % 100000) == 0) { 297 std::cerr << "Warning: " 298 << req->xc->storeCondFailures 299 << " consecutive store conditional failures " 300 << "on cpu " << req->xc->cpu_id 301 << std::endl; 302 } 303 return No_Fault; 304 } 305 else req->xc->storeCondFailures = 0; 306 } 307 } 308 309 // Need to clear any locked flags on other proccessors for 310 // this address. Only do this for succsful Store Conditionals 311 // and all other stores (WH64?). Unsuccessful Store 312 // Conditionals would have returned above, and wouldn't fall 313 // through. 314 for (int i = 0; i < system->execContexts.size(); i++){ 315 cregs = &system->execContexts[i]->regs.miscRegs; 316 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 317 cregs->lock_flag = false; 318 } 319 } 320 321#endif 322 return mem->write(req, (T)LittleEndianGuest::htog(data)); 323 } 324 325 virtual bool misspeculating(); 326 327 328 MachInst getInst() { return inst; } 329 330 void setInst(MachInst new_inst) 331 { 332 inst = new_inst; 333 } 334 335 Fault instRead(MemReqPtr &req) 336 { 337 return mem->read(req, inst); 338 } 339 340 // 341 // New accessors for new decoder. 342 // 343 uint64_t readIntReg(int reg_idx) 344 { 345 return regs.intRegFile[reg_idx]; 346 } 347 348 float readFloatRegSingle(int reg_idx) 349 { 350 return (float)regs.floatRegFile.d[reg_idx]; 351 } 352 353 double readFloatRegDouble(int reg_idx) 354 { 355 return regs.floatRegFile.d[reg_idx]; 356 } 357 358 uint64_t readFloatRegInt(int reg_idx) 359 { 360 return regs.floatRegFile.q[reg_idx]; 361 } 362 363 void setIntReg(int reg_idx, uint64_t val) 364 { 365 regs.intRegFile[reg_idx] = val; 366 } 367 368 void setFloatRegSingle(int reg_idx, float val) 369 { 370 regs.floatRegFile.d[reg_idx] = (double)val; 371 } 372 373 void setFloatRegDouble(int reg_idx, double val) 374 { 375 regs.floatRegFile.d[reg_idx] = val; 376 } 377 378 void setFloatRegInt(int reg_idx, uint64_t val) 379 { 380 regs.floatRegFile.q[reg_idx] = val; 381 } 382 383 uint64_t readPC() 384 { 385 return regs.pc; 386 } 387 388 void setNextPC(uint64_t val) 389 { 390 regs.npc = val; 391 } 392 393 uint64_t readUniq() 394 { 395 return regs.miscRegs.uniq; 396 } 397 398 void setUniq(uint64_t val) 399 { 400 regs.miscRegs.uniq = val; 401 } 402 403 uint64_t readFpcr() 404 { 405 return regs.miscRegs.fpcr; 406 } 407 408 void setFpcr(uint64_t val) 409 { 410 regs.miscRegs.fpcr = val; 411 } 412 413#if FULL_SYSTEM 414 uint64_t readIpr(int idx, Fault &fault); 415 Fault setIpr(int idx, uint64_t val); 416 int readIntrFlag() { return regs.intrflag; } 417 void setIntrFlag(int val) { regs.intrflag = val; } 418 Fault hwrei(); 419 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 420 void ev5_trap(Fault fault); 421 bool simPalCheck(int palFunc); 422#endif 423 424 /** Meant to be more generic trap function to be 425 * called when an instruction faults. 426 * @param fault The fault generated by executing the instruction. 427 * @todo How to do this properly so it's dependent upon ISA only? 428 */ 429 430 void trap(Fault fault); 431 432#if !FULL_SYSTEM 433 IntReg getSyscallArg(int i) 434 { 435 return regs.intRegFile[ArgumentReg0 + i]; 436 } 437 438 // used to shift args for indirect syscall 439 void setSyscallArg(int i, IntReg val) 440 { 441 regs.intRegFile[ArgumentReg0 + i] = val; 442 } 443 444 void setSyscallReturn(SyscallReturn return_value) 445 { 446 // check for error condition. Alpha syscall convention is to 447 // indicate success/failure in reg a3 (r19) and put the 448 // return value itself in the standard return value reg (v0). 449 const int RegA3 = 19; // only place this is used 450 if (return_value.successful()) { 451 // no error 452 regs.intRegFile[RegA3] = 0; 453 regs.intRegFile[ReturnValueReg] = return_value.value(); 454 } else { 455 // got an error, return details 456 regs.intRegFile[RegA3] = (IntReg) -1; 457 regs.intRegFile[ReturnValueReg] = -return_value.value(); 458 } 459 } 460 461 void syscall() 462 { 463 process->syscall(this); 464 } 465#endif 466}; 467 468 469// for non-speculative execution context, spec_mode is always false 470inline bool 471ExecContext::misspeculating() 472{ 473 return false; 474} 475 476#endif // __CPU_EXEC_CONTEXT_HH__ 477