thread_context.hh revision 13865
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 6013693Sgiacomo.gabrielli@arm.com class ISA; 619020Sgblack@eecs.umich.edu class Decoder; 623453Sgblack@eecs.umich.edu} 632190SN/Aclass BaseCPU; 6412406Sgabeblack@google.comclass BaseTLB; 658887Sgeoffrey.blake@arm.comclass CheckerCPU; 667680Sgblack@eecs.umich.educlass Checkpoint; 672313SN/Aclass EndQuiesceEvent; 688706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 698706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 708706Sandreas.hansson@arm.comclass PortProxy; 712190SN/Aclass Process; 722190SN/Aclass System; 733548Sgblack@eecs.umich.edunamespace TheISA { 743548Sgblack@eecs.umich.edu namespace Kernel { 753548Sgblack@eecs.umich.edu class Statistics; 768902Sandreas.hansson@arm.com } 778902Sandreas.hansson@arm.com} 782SN/A 792680Sktlim@umich.edu/** 802680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 812680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 822680Sktlim@umich.edu * state that might be needed by external objects, ranging from 832680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 8413865Sgabeblack@google.com * base class; the CPU can create its own ThreadContext by 8513865Sgabeblack@google.com * deriving from it. 862680Sktlim@umich.edu * 872680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 882680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 892680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 902682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 912680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 922680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 932680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 942680Sktlim@umich.edu */ 952680Sktlim@umich.educlass ThreadContext 962SN/A{ 972107SN/A protected: 982107SN/A typedef TheISA::MachInst MachInst; 9912109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10012109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10113610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 10213610Sgiacomo.gabrielli@arm.com 1032SN/A public: 1046029Ssteve.reinhardt@amd.com 105246SN/A enum Status 106246SN/A { 107246SN/A /// Running. Instructions should be executed only when 108246SN/A /// the context is in this state. 109246SN/A Active, 110246SN/A 111246SN/A /// Temporarily inactive. Entered while waiting for 1122190SN/A /// synchronization, etc. 113246SN/A Suspended, 114246SN/A 11513641Sqtt2@cornell.edu /// Trying to exit and waiting for an event to completely exit. 11613641Sqtt2@cornell.edu /// Entered when target executes an exit syscall. 11713641Sqtt2@cornell.edu Halting, 11813641Sqtt2@cornell.edu 119246SN/A /// Permanently shut down. Entered when target executes 120246SN/A /// m5exit pseudo-instruction. When all contexts enter 121246SN/A /// this state, the simulation will terminate. 122246SN/A Halted 123246SN/A }; 1242SN/A 1252680Sktlim@umich.edu virtual ~ThreadContext() { }; 1262423SN/A 1272190SN/A virtual BaseCPU *getCpuPtr() = 0; 128180SN/A 12910110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1302190SN/A 13110190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 13210190Sakash.bagdia@arm.com 13310110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1345715Shsul@eecs.umich.edu 1355715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1365714Shsul@eecs.umich.edu 13713865Sgabeblack@google.com virtual ContextID contextId() const = 0; 1385714Shsul@eecs.umich.edu 13913865Sgabeblack@google.com virtual void setContextId(ContextID id) = 0; 1405714Shsul@eecs.umich.edu 14112406Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 1422190SN/A 14312406Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 1442521SN/A 1458887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1468733Sgeoffrey.blake@arm.com 14713693Sgiacomo.gabrielli@arm.com virtual TheISA::ISA *getIsaPtr() = 0; 14813693Sgiacomo.gabrielli@arm.com 1499020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1508541Sgblack@eecs.umich.edu 1514997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1524997Sgblack@eecs.umich.edu 1533548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1542654SN/A 1558852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1562521SN/A 1578852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1583673Srdreslin@umich.edu 1598706Sandreas.hansson@arm.com /** 1608706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1618706Sandreas.hansson@arm.com * the data port of the CPU. 1628706Sandreas.hansson@arm.com * 1638706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1648706Sandreas.hansson@arm.com */ 1658706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1668799Sgblack@eecs.umich.edu 1678852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1682518SN/A 1692190SN/A virtual Process *getProcessPtr() = 0; 1702190SN/A 17111886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 17211886Sbrandon.potter@amd.com 1732190SN/A virtual Status status() const = 0; 1742159SN/A 1752235SN/A virtual void setStatus(Status new_status) = 0; 1762103SN/A 17710407Smitch.hayenga@arm.com /// Set the status to Active. 17810407Smitch.hayenga@arm.com virtual void activate() = 0; 179393SN/A 180393SN/A /// Set the status to Suspended. 18110407Smitch.hayenga@arm.com virtual void suspend() = 0; 182393SN/A 183393SN/A /// Set the status to Halted. 18410407Smitch.hayenga@arm.com virtual void halt() = 0; 1852159SN/A 18611627Smichael.lebeane@amd.com /// Quiesce thread context 18711627Smichael.lebeane@amd.com void quiesce(); 18811627Smichael.lebeane@amd.com 18911627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 19011627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 19111627Smichael.lebeane@amd.com 1922190SN/A virtual void dumpFuncProfile() = 0; 1932159SN/A 1942680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1952159SN/A 1962190SN/A virtual void regStats(const std::string &name) = 0; 1972159SN/A 1982313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1992235SN/A 2002235SN/A // Not necessarily the best location for these... 2012235SN/A // Having an extra function just to read these is obnoxious 2022235SN/A virtual Tick readLastActivate() = 0; 2032235SN/A virtual Tick readLastSuspend() = 0; 2042254SN/A 2052254SN/A virtual void profileClear() = 0; 2062254SN/A virtual void profileSample() = 0; 2072235SN/A 2082680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2092159SN/A 2102190SN/A virtual void clearArchRegs() = 0; 2112159SN/A 2122159SN/A // 2132159SN/A // New accessors for new decoder. 2142159SN/A // 21513865Sgabeblack@google.com virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 2162159SN/A 21713865Sgabeblack@google.com virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 2182159SN/A 21912109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 22012109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 22112109SRekai.GonzalezAlberquilla@arm.com 22212109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22312109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 22612109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const = 0; 22712109SRekai.GonzalezAlberquilla@arm.com 22812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 23012109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const = 0; 23112109SRekai.GonzalezAlberquilla@arm.com 23212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23312109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 23412109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const = 0; 23512109SRekai.GonzalezAlberquilla@arm.com 23612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 23712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 23812109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const = 0; 23912109SRekai.GonzalezAlberquilla@arm.com 24012109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 24112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 24312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 24512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 24712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 24912109SRekai.GonzalezAlberquilla@arm.com /** @} */ 25012109SRekai.GonzalezAlberquilla@arm.com 25112109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 25212109SRekai.GonzalezAlberquilla@arm.com 25313610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 25413610Sgiacomo.gabrielli@arm.com const = 0; 25513610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 25613610Sgiacomo.gabrielli@arm.com 25713865Sgabeblack@google.com virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 2589920Syasuko.eckert@amd.com 25913865Sgabeblack@google.com virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 2602159SN/A 26113865Sgabeblack@google.com virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 2622455SN/A 26312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 26412109SRekai.GonzalezAlberquilla@arm.com 26512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 26612109SRekai.GonzalezAlberquilla@arm.com 26713610Sgiacomo.gabrielli@arm.com virtual void setVecPredReg(const RegId& reg, 26813610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 26913610Sgiacomo.gabrielli@arm.com 27013865Sgabeblack@google.com virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 2719920Syasuko.eckert@amd.com 27213865Sgabeblack@google.com virtual TheISA::PCState pcState() const = 0; 2732159SN/A 2747720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2752159SN/A 27611886Sbrandon.potter@amd.com void 27711886Sbrandon.potter@amd.com setNPC(Addr val) 27811886Sbrandon.potter@amd.com { 27911886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 28011886Sbrandon.potter@amd.com pc_state.setNPC(val); 28111886Sbrandon.potter@amd.com pcState(pc_state); 28211886Sbrandon.potter@amd.com } 28311886Sbrandon.potter@amd.com 2848733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2858733Sgeoffrey.blake@arm.com 28613865Sgabeblack@google.com virtual Addr instAddr() const = 0; 2872159SN/A 28813865Sgabeblack@google.com virtual Addr nextInstAddr() const = 0; 2892159SN/A 29013865Sgabeblack@google.com virtual MicroPC microPC() const = 0; 2915260Sksewell@umich.edu 29213865Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 2934172Ssaidi@eecs.umich.edu 29413865Sgabeblack@google.com virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 2952159SN/A 29613865Sgabeblack@google.com virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 2972190SN/A 29813865Sgabeblack@google.com virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0; 2992190SN/A 30012106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 3016313Sgblack@eecs.umich.edu 30213557Sgabeblack@google.com virtual RegVal 30312106SRekai.GonzalezAlberquilla@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 3046221Snate@binkert.org { 3056221Snate@binkert.org return 0; 3066221Snate@binkert.org } 3074661Sksewell@umich.edu 3086221Snate@binkert.org virtual void 30913582Sgabeblack@google.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 3106221Snate@binkert.org { 3116221Snate@binkert.org } 3124661Sksewell@umich.edu 3132235SN/A // Also not necessarily the best location for these two. Hopefully will go 3142235SN/A // away once we decide upon where st cond failures goes. 31513865Sgabeblack@google.com virtual unsigned readStCondFailures() const = 0; 3162190SN/A 3172190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 3182159SN/A 3192235SN/A // Same with st cond failures. 32013865Sgabeblack@google.com virtual Counter readFuncExeInst() const = 0; 3212834Sksewell@umich.edu 32211877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 3234111Sgblack@eecs.umich.edu 3242834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 3252834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 3262834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 3272834Sksewell@umich.edu virtual int exit() { return 1; }; 3282525SN/A 3295217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 3305217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 3319426SAndreas.Sandberg@ARM.com 3329426SAndreas.Sandberg@ARM.com /** @{ */ 3339426SAndreas.Sandberg@ARM.com /** 3349426SAndreas.Sandberg@ARM.com * Flat register interfaces 3359426SAndreas.Sandberg@ARM.com * 3369426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 3379426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 33812106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 3399426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 3409426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 3419426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 3429426SAndreas.Sandberg@ARM.com */ 3439426SAndreas.Sandberg@ARM.com 34413865Sgabeblack@google.com virtual RegVal readIntRegFlat(RegIndex idx) const = 0; 34513865Sgabeblack@google.com virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0; 3469426SAndreas.Sandberg@ARM.com 34713865Sgabeblack@google.com virtual RegVal readFloatRegFlat(RegIndex idx) const = 0; 34813865Sgabeblack@google.com virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0; 3499426SAndreas.Sandberg@ARM.com 35013865Sgabeblack@google.com virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0; 35113865Sgabeblack@google.com virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0; 35213865Sgabeblack@google.com virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0; 35312109SRekai.GonzalezAlberquilla@arm.com 35413865Sgabeblack@google.com virtual const VecElem& readVecElemFlat(RegIndex idx, 35512109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIdx) const = 0; 35613865Sgabeblack@google.com virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 35712109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) = 0; 35812109SRekai.GonzalezAlberquilla@arm.com 35913865Sgabeblack@google.com virtual const VecPredRegContainer & 36013865Sgabeblack@google.com readVecPredRegFlat(RegIndex idx) const = 0; 36113865Sgabeblack@google.com virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0; 36213865Sgabeblack@google.com virtual void setVecPredRegFlat(RegIndex idx, 36313610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 36413610Sgiacomo.gabrielli@arm.com 36513865Sgabeblack@google.com virtual RegVal readCCRegFlat(RegIndex idx) const = 0; 36613865Sgabeblack@google.com virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0; 3679426SAndreas.Sandberg@ARM.com /** @} */ 3689426SAndreas.Sandberg@ARM.com 3692159SN/A}; 3702159SN/A 3719428SAndreas.Sandberg@ARM.com/** @{ */ 3729428SAndreas.Sandberg@ARM.com/** 3739428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 3749428SAndreas.Sandberg@ARM.com * 3759428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 3769428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 3779428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 3789428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 3799428SAndreas.Sandberg@ARM.com */ 3809428SAndreas.Sandberg@ARM.com 38113865Sgabeblack@google.comvoid serialize(const ThreadContext &tc, CheckpointOut &cp); 38210905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 3839428SAndreas.Sandberg@ARM.com 3849428SAndreas.Sandberg@ARM.com/** @} */ 3859428SAndreas.Sandberg@ARM.com 3869441SAndreas.Sandberg@ARM.com 3879441SAndreas.Sandberg@ARM.com/** 3889441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 3899441SAndreas.Sandberg@ARM.com * 3909441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 3919441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 3929441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 3939441SAndreas.Sandberg@ARM.com * 3949441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 3959441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 3969441SAndreas.Sandberg@ARM.com */ 3979441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 3989441SAndreas.Sandberg@ARM.com 3992190SN/A#endif 400