thread_context.hh revision 13865
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 312855Sgabeblack@google.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412855Sgabeblack@google.com * All rights reserved 512855Sgabeblack@google.com * 612855Sgabeblack@google.com * The license below extends only to copyright in the software and shall 712855Sgabeblack@google.com * not be construed as granting a license to any other intellectual 812855Sgabeblack@google.com * property including but not limited to intellectual property relating 912855Sgabeblack@google.com * to a hardware implementation of the functionality of the software 1012855Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1112855Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1212855Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1312855Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1412855Sgabeblack@google.com * 1512855Sgabeblack@google.com * Copyright (c) 2006 The Regents of The University of Michigan 1612855Sgabeblack@google.com * All rights reserved. 1712855Sgabeblack@google.com * 1812855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1912855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 2012855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2112855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2212855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2312855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2412855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2512855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2612855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2712855Sgabeblack@google.com * this software without specific prior written permission. 2812855Sgabeblack@google.com * 2912855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012855Sgabeblack@google.com * 4112855Sgabeblack@google.com * Authors: Kevin Lim 4212855Sgabeblack@google.com */ 4312855Sgabeblack@google.com 4412855Sgabeblack@google.com#ifndef __CPU_THREAD_CONTEXT_HH__ 4512855Sgabeblack@google.com#define __CPU_THREAD_CONTEXT_HH__ 4612855Sgabeblack@google.com 4712855Sgabeblack@google.com#include <iostream> 4812855Sgabeblack@google.com#include <string> 4912855Sgabeblack@google.com 5012855Sgabeblack@google.com#include "arch/registers.hh" 5112855Sgabeblack@google.com#include "arch/types.hh" 5212855Sgabeblack@google.com#include "base/types.hh" 5312855Sgabeblack@google.com#include "config/the_isa.hh" 5412855Sgabeblack@google.com#include "cpu/reg_class.hh" 5512855Sgabeblack@google.com 5612855Sgabeblack@google.com// @todo: Figure out a more architecture independent way to obtain the ITB and 5712855Sgabeblack@google.com// DTB pointers. 5812855Sgabeblack@google.comnamespace TheISA 5912855Sgabeblack@google.com{ 6012855Sgabeblack@google.com class ISA; 6112855Sgabeblack@google.com class Decoder; 6212855Sgabeblack@google.com} 6312855Sgabeblack@google.comclass BaseCPU; 6412855Sgabeblack@google.comclass BaseTLB; 6512855Sgabeblack@google.comclass CheckerCPU; 6612855Sgabeblack@google.comclass Checkpoint; 6712855Sgabeblack@google.comclass EndQuiesceEvent; 6812855Sgabeblack@google.comclass SETranslatingPortProxy; 6912855Sgabeblack@google.comclass FSTranslatingPortProxy; 7012855Sgabeblack@google.comclass PortProxy; 7112855Sgabeblack@google.comclass Process; 7212855Sgabeblack@google.comclass System; 7312855Sgabeblack@google.comnamespace TheISA { 7412855Sgabeblack@google.com namespace Kernel { 7512855Sgabeblack@google.com class Statistics; 7612855Sgabeblack@google.com } 7712855Sgabeblack@google.com} 7812855Sgabeblack@google.com 7912855Sgabeblack@google.com/** 8012855Sgabeblack@google.com * ThreadContext is the external interface to all thread state for 8112855Sgabeblack@google.com * anything outside of the CPU. It provides all accessor methods to 8212855Sgabeblack@google.com * state that might be needed by external objects, ranging from 8312855Sgabeblack@google.com * register values to things such as kernel stats. It is an abstract 8412855Sgabeblack@google.com * base class; the CPU can create its own ThreadContext by 8512855Sgabeblack@google.com * deriving from it. 8612855Sgabeblack@google.com * 8712855Sgabeblack@google.com * The ThreadContext is slightly different than the ExecContext. The 8812855Sgabeblack@google.com * ThreadContext provides access to an individual thread's state; an 8912855Sgabeblack@google.com * ExecContext provides ISA access to the CPU (meaning it is 9012855Sgabeblack@google.com * implicitly multithreaded on SMT systems). Additionally the 9112855Sgabeblack@google.com * ThreadState is an abstract class that exactly defines the 9212855Sgabeblack@google.com * interface; the ExecContext is a more implicit interface that must 9312855Sgabeblack@google.com * be implemented so that the ISA can access whatever state it needs. 9412855Sgabeblack@google.com */ 9512855Sgabeblack@google.comclass ThreadContext 9612855Sgabeblack@google.com{ 9712855Sgabeblack@google.com protected: 9812855Sgabeblack@google.com typedef TheISA::MachInst MachInst; 9912855Sgabeblack@google.com using VecRegContainer = TheISA::VecRegContainer; 10012855Sgabeblack@google.com using VecElem = TheISA::VecElem; 10112855Sgabeblack@google.com using VecPredRegContainer = TheISA::VecPredRegContainer; 10212855Sgabeblack@google.com 10312855Sgabeblack@google.com public: 10412855Sgabeblack@google.com 10512855Sgabeblack@google.com enum Status 10612855Sgabeblack@google.com { 10712855Sgabeblack@google.com /// Running. Instructions should be executed only when 10812855Sgabeblack@google.com /// the context is in this state. 10912855Sgabeblack@google.com Active, 11012855Sgabeblack@google.com 11112855Sgabeblack@google.com /// Temporarily inactive. Entered while waiting for 11212855Sgabeblack@google.com /// synchronization, etc. 11312855Sgabeblack@google.com Suspended, 11412855Sgabeblack@google.com 11512855Sgabeblack@google.com /// Trying to exit and waiting for an event to completely exit. 11612855Sgabeblack@google.com /// Entered when target executes an exit syscall. 11712855Sgabeblack@google.com Halting, 11812855Sgabeblack@google.com 11912855Sgabeblack@google.com /// Permanently shut down. Entered when target executes 12012855Sgabeblack@google.com /// m5exit pseudo-instruction. When all contexts enter 12112855Sgabeblack@google.com /// this state, the simulation will terminate. 12212855Sgabeblack@google.com Halted 12312855Sgabeblack@google.com }; 12412855Sgabeblack@google.com 12512855Sgabeblack@google.com virtual ~ThreadContext() { }; 12612855Sgabeblack@google.com 12712855Sgabeblack@google.com virtual BaseCPU *getCpuPtr() = 0; 12812855Sgabeblack@google.com 12912855Sgabeblack@google.com virtual int cpuId() const = 0; 13012855Sgabeblack@google.com 13112855Sgabeblack@google.com virtual uint32_t socketId() const = 0; 13212855Sgabeblack@google.com 13312855Sgabeblack@google.com virtual int threadId() const = 0; 13412855Sgabeblack@google.com 13512855Sgabeblack@google.com virtual void setThreadId(int id) = 0; 13612855Sgabeblack@google.com 13712855Sgabeblack@google.com virtual ContextID contextId() const = 0; 13812855Sgabeblack@google.com 13912855Sgabeblack@google.com virtual void setContextId(ContextID id) = 0; 14012855Sgabeblack@google.com 14112855Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 14212855Sgabeblack@google.com 14312855Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 14412855Sgabeblack@google.com 14512855Sgabeblack@google.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 14612855Sgabeblack@google.com 14712855Sgabeblack@google.com virtual TheISA::ISA *getIsaPtr() = 0; 14812855Sgabeblack@google.com 14912855Sgabeblack@google.com virtual TheISA::Decoder *getDecoderPtr() = 0; 15012855Sgabeblack@google.com 15112855Sgabeblack@google.com virtual System *getSystemPtr() = 0; 15212855Sgabeblack@google.com 15312855Sgabeblack@google.com virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 15412855Sgabeblack@google.com 15512855Sgabeblack@google.com virtual PortProxy &getPhysProxy() = 0; 15612855Sgabeblack@google.com 15712855Sgabeblack@google.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 15812855Sgabeblack@google.com 15912855Sgabeblack@google.com /** 16012855Sgabeblack@google.com * Initialise the physical and virtual port proxies and tie them to 16112855Sgabeblack@google.com * the data port of the CPU. 16212855Sgabeblack@google.com * 16312855Sgabeblack@google.com * tc ThreadContext for the virtual-to-physical translation 16412855Sgabeblack@google.com */ 16512855Sgabeblack@google.com virtual void initMemProxies(ThreadContext *tc) = 0; 16612855Sgabeblack@google.com 16712855Sgabeblack@google.com virtual SETranslatingPortProxy &getMemProxy() = 0; 16812855Sgabeblack@google.com 16912855Sgabeblack@google.com virtual Process *getProcessPtr() = 0; 17012855Sgabeblack@google.com 17112855Sgabeblack@google.com virtual void setProcessPtr(Process *p) = 0; 17212855Sgabeblack@google.com 17312855Sgabeblack@google.com virtual Status status() const = 0; 17412855Sgabeblack@google.com 17512855Sgabeblack@google.com virtual void setStatus(Status new_status) = 0; 17612855Sgabeblack@google.com 17712855Sgabeblack@google.com /// Set the status to Active. 17812855Sgabeblack@google.com virtual void activate() = 0; 17912855Sgabeblack@google.com 18012855Sgabeblack@google.com /// Set the status to Suspended. 18112855Sgabeblack@google.com virtual void suspend() = 0; 18212855Sgabeblack@google.com 18312855Sgabeblack@google.com /// Set the status to Halted. 18412855Sgabeblack@google.com virtual void halt() = 0; 18512855Sgabeblack@google.com 18612855Sgabeblack@google.com /// Quiesce thread context 18712855Sgabeblack@google.com void quiesce(); 18812855Sgabeblack@google.com 18912855Sgabeblack@google.com /// Quiesce, suspend, and schedule activate at resume 19012855Sgabeblack@google.com void quiesceTick(Tick resume); 19112855Sgabeblack@google.com 19212855Sgabeblack@google.com virtual void dumpFuncProfile() = 0; 19312855Sgabeblack@google.com 19412855Sgabeblack@google.com virtual void takeOverFrom(ThreadContext *old_context) = 0; 19512855Sgabeblack@google.com 19612855Sgabeblack@google.com virtual void regStats(const std::string &name) = 0; 19712855Sgabeblack@google.com 19812855Sgabeblack@google.com virtual EndQuiesceEvent *getQuiesceEvent() = 0; 19912855Sgabeblack@google.com 20012855Sgabeblack@google.com // Not necessarily the best location for these... 20112855Sgabeblack@google.com // Having an extra function just to read these is obnoxious 20212855Sgabeblack@google.com virtual Tick readLastActivate() = 0; 20312855Sgabeblack@google.com virtual Tick readLastSuspend() = 0; 20412855Sgabeblack@google.com 20512855Sgabeblack@google.com virtual void profileClear() = 0; 20612855Sgabeblack@google.com virtual void profileSample() = 0; 20712855Sgabeblack@google.com 20812855Sgabeblack@google.com virtual void copyArchRegs(ThreadContext *tc) = 0; 20912855Sgabeblack@google.com 21012855Sgabeblack@google.com virtual void clearArchRegs() = 0; 21112855Sgabeblack@google.com 21212855Sgabeblack@google.com // 21312855Sgabeblack@google.com // New accessors for new decoder. 21412855Sgabeblack@google.com // 21512855Sgabeblack@google.com virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 21612855Sgabeblack@google.com 21712855Sgabeblack@google.com virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 21812855Sgabeblack@google.com 21912855Sgabeblack@google.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 22012855Sgabeblack@google.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 22112855Sgabeblack@google.com 22212855Sgabeblack@google.com /** Vector Register Lane Interfaces. */ 22312855Sgabeblack@google.com /** @{ */ 22412855Sgabeblack@google.com /** Reads source vector 8bit operand. */ 22512855Sgabeblack@google.com virtual ConstVecLane8 22612855Sgabeblack@google.com readVec8BitLaneReg(const RegId& reg) const = 0; 22712855Sgabeblack@google.com 22812855Sgabeblack@google.com /** Reads source vector 16bit operand. */ 22912855Sgabeblack@google.com virtual ConstVecLane16 23012855Sgabeblack@google.com readVec16BitLaneReg(const RegId& reg) const = 0; 23112855Sgabeblack@google.com 23212855Sgabeblack@google.com /** Reads source vector 32bit operand. */ 23312855Sgabeblack@google.com virtual ConstVecLane32 23412855Sgabeblack@google.com readVec32BitLaneReg(const RegId& reg) const = 0; 23512855Sgabeblack@google.com 23612855Sgabeblack@google.com /** Reads source vector 64bit operand. */ 23712855Sgabeblack@google.com virtual ConstVecLane64 23812855Sgabeblack@google.com readVec64BitLaneReg(const RegId& reg) const = 0; 23912855Sgabeblack@google.com 24012855Sgabeblack@google.com /** Write a lane of the destination vector register. */ 24112855Sgabeblack@google.com virtual void setVecLane(const RegId& reg, 24212855Sgabeblack@google.com const LaneData<LaneSize::Byte>& val) = 0; 24312855Sgabeblack@google.com virtual void setVecLane(const RegId& reg, 24412855Sgabeblack@google.com const LaneData<LaneSize::TwoByte>& val) = 0; 24512855Sgabeblack@google.com virtual void setVecLane(const RegId& reg, 24612855Sgabeblack@google.com const LaneData<LaneSize::FourByte>& val) = 0; 24712855Sgabeblack@google.com virtual void setVecLane(const RegId& reg, 24812855Sgabeblack@google.com const LaneData<LaneSize::EightByte>& val) = 0; 24912855Sgabeblack@google.com /** @} */ 25012855Sgabeblack@google.com 25112855Sgabeblack@google.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 25212855Sgabeblack@google.com 25312855Sgabeblack@google.com virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 25412855Sgabeblack@google.com const = 0; 25512855Sgabeblack@google.com virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 25612855Sgabeblack@google.com 25712855Sgabeblack@google.com virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 25812855Sgabeblack@google.com 25912855Sgabeblack@google.com virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 26012855Sgabeblack@google.com 26112855Sgabeblack@google.com virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 26212855Sgabeblack@google.com 26312855Sgabeblack@google.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 26412855Sgabeblack@google.com 26512855Sgabeblack@google.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 26612855Sgabeblack@google.com 26712855Sgabeblack@google.com virtual void setVecPredReg(const RegId& reg, 26812855Sgabeblack@google.com const VecPredRegContainer& val) = 0; 26912855Sgabeblack@google.com 27012855Sgabeblack@google.com virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 27112855Sgabeblack@google.com 27212855Sgabeblack@google.com virtual TheISA::PCState pcState() const = 0; 27312855Sgabeblack@google.com 27412855Sgabeblack@google.com virtual void pcState(const TheISA::PCState &val) = 0; 27512855Sgabeblack@google.com 27612855Sgabeblack@google.com void 27712855Sgabeblack@google.com setNPC(Addr val) 27812855Sgabeblack@google.com { 27912855Sgabeblack@google.com TheISA::PCState pc_state = pcState(); 28012855Sgabeblack@google.com pc_state.setNPC(val); 28112855Sgabeblack@google.com pcState(pc_state); 28212855Sgabeblack@google.com } 28312855Sgabeblack@google.com 28412855Sgabeblack@google.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 28512855Sgabeblack@google.com 28612855Sgabeblack@google.com virtual Addr instAddr() const = 0; 28712855Sgabeblack@google.com 28812855Sgabeblack@google.com virtual Addr nextInstAddr() const = 0; 28912855Sgabeblack@google.com 29012855Sgabeblack@google.com virtual MicroPC microPC() const = 0; 29112855Sgabeblack@google.com 29212855Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 29312855Sgabeblack@google.com 29412855Sgabeblack@google.com virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 29512855Sgabeblack@google.com 29612855Sgabeblack@google.com virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 29712855Sgabeblack@google.com 29812855Sgabeblack@google.com virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0; 29912855Sgabeblack@google.com 30012855Sgabeblack@google.com virtual RegId flattenRegId(const RegId& regId) const = 0; 30112855Sgabeblack@google.com 30212855Sgabeblack@google.com virtual RegVal 30312855Sgabeblack@google.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 30412855Sgabeblack@google.com { 30512855Sgabeblack@google.com return 0; 30612855Sgabeblack@google.com } 30712855Sgabeblack@google.com 30812855Sgabeblack@google.com virtual void 30912855Sgabeblack@google.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 31012855Sgabeblack@google.com { 31112855Sgabeblack@google.com } 31212855Sgabeblack@google.com 31312855Sgabeblack@google.com // Also not necessarily the best location for these two. Hopefully will go 31412855Sgabeblack@google.com // away once we decide upon where st cond failures goes. 31512855Sgabeblack@google.com virtual unsigned readStCondFailures() const = 0; 31612855Sgabeblack@google.com 31712855Sgabeblack@google.com virtual void setStCondFailures(unsigned sc_failures) = 0; 31812855Sgabeblack@google.com 31912855Sgabeblack@google.com // Same with st cond failures. 32012855Sgabeblack@google.com virtual Counter readFuncExeInst() const = 0; 32112855Sgabeblack@google.com 32212855Sgabeblack@google.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 32312855Sgabeblack@google.com 32412855Sgabeblack@google.com // This function exits the thread context in the CPU and returns 32512855Sgabeblack@google.com // 1 if the CPU has no more active threads (meaning it's OK to exit); 32612855Sgabeblack@google.com // Used in syscall-emulation mode when a thread calls the exit syscall. 32712855Sgabeblack@google.com virtual int exit() { return 1; }; 32812855Sgabeblack@google.com 32912855Sgabeblack@google.com /** function to compare two thread contexts (for debugging) */ 33012855Sgabeblack@google.com static void compare(ThreadContext *one, ThreadContext *two); 33112855Sgabeblack@google.com 33212855Sgabeblack@google.com /** @{ */ 33312855Sgabeblack@google.com /** 33412855Sgabeblack@google.com * Flat register interfaces 33512855Sgabeblack@google.com * 33612855Sgabeblack@google.com * Some architectures have different registers visible in 33712855Sgabeblack@google.com * different modes. Such architectures "flatten" a register (see 33812855Sgabeblack@google.com * flattenRegId()) to map it into the 33912855Sgabeblack@google.com * gem5 register file. This interface provides a flat interface to 34012855Sgabeblack@google.com * the underlying register file, which allows for example 34112855Sgabeblack@google.com * serialization code to access all registers. 34212855Sgabeblack@google.com */ 34312855Sgabeblack@google.com 34412855Sgabeblack@google.com virtual RegVal readIntRegFlat(RegIndex idx) const = 0; 34512855Sgabeblack@google.com virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0; 34612855Sgabeblack@google.com 34712855Sgabeblack@google.com virtual RegVal readFloatRegFlat(RegIndex idx) const = 0; 34812855Sgabeblack@google.com virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0; 34912855Sgabeblack@google.com 35012855Sgabeblack@google.com virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0; 35112855Sgabeblack@google.com virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0; 35212855Sgabeblack@google.com virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0; 35312855Sgabeblack@google.com 35412855Sgabeblack@google.com virtual const VecElem& readVecElemFlat(RegIndex idx, 35512855Sgabeblack@google.com const ElemIndex& elemIdx) const = 0; 35612855Sgabeblack@google.com virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 35712855Sgabeblack@google.com const VecElem& val) = 0; 35812855Sgabeblack@google.com 35912855Sgabeblack@google.com virtual const VecPredRegContainer & 36012855Sgabeblack@google.com readVecPredRegFlat(RegIndex idx) const = 0; 36112855Sgabeblack@google.com virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0; 36212855Sgabeblack@google.com virtual void setVecPredRegFlat(RegIndex idx, 36312855Sgabeblack@google.com const VecPredRegContainer& val) = 0; 36412855Sgabeblack@google.com 36512855Sgabeblack@google.com virtual RegVal readCCRegFlat(RegIndex idx) const = 0; 36612855Sgabeblack@google.com virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0; 36712855Sgabeblack@google.com /** @} */ 36812855Sgabeblack@google.com 36912855Sgabeblack@google.com}; 37012855Sgabeblack@google.com 37112855Sgabeblack@google.com/** @{ */ 37212855Sgabeblack@google.com/** 37312855Sgabeblack@google.com * Thread context serialization helpers 37412855Sgabeblack@google.com * 37512855Sgabeblack@google.com * These helper functions provide a way to the data in a 37612855Sgabeblack@google.com * ThreadContext. They are provided as separate helper function since 37712855Sgabeblack@google.com * implementing them as members of the ThreadContext interface would 37812855Sgabeblack@google.com * be confusing when the ThreadContext is exported via a proxy. 37912855Sgabeblack@google.com */ 38012855Sgabeblack@google.com 38112855Sgabeblack@google.comvoid serialize(const ThreadContext &tc, CheckpointOut &cp); 38212855Sgabeblack@google.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 38312855Sgabeblack@google.com 38412855Sgabeblack@google.com/** @} */ 38512855Sgabeblack@google.com 38612855Sgabeblack@google.com 38712855Sgabeblack@google.com/** 38812855Sgabeblack@google.com * Copy state between thread contexts in preparation for CPU handover. 38912855Sgabeblack@google.com * 39012855Sgabeblack@google.com * @note This method modifies the old thread contexts as well as the 39112855Sgabeblack@google.com * new thread context. The old thread context will have its quiesce 39212855Sgabeblack@google.com * event descheduled if it is scheduled and its status set to halted. 39312855Sgabeblack@google.com * 39412855Sgabeblack@google.com * @param new_tc Destination ThreadContext. 39512855Sgabeblack@google.com * @param old_tc Source ThreadContext. 39612855Sgabeblack@google.com */ 39712855Sgabeblack@google.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 39812855Sgabeblack@google.com 39912855Sgabeblack@google.com#endif 40012855Sgabeblack@google.com