thread_context.hh revision 13582
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 609020Sgblack@eecs.umich.edu class Decoder; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 6312406Sgabeblack@google.comclass BaseTLB; 648887Sgeoffrey.blake@arm.comclass CheckerCPU; 657680Sgblack@eecs.umich.educlass Checkpoint; 662313SN/Aclass EndQuiesceEvent; 678706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 688706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 698706Sandreas.hansson@arm.comclass PortProxy; 702190SN/Aclass Process; 712190SN/Aclass System; 723548Sgblack@eecs.umich.edunamespace TheISA { 733548Sgblack@eecs.umich.edu namespace Kernel { 743548Sgblack@eecs.umich.edu class Statistics; 758902Sandreas.hansson@arm.com } 768902Sandreas.hansson@arm.com} 772SN/A 782680Sktlim@umich.edu/** 792680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 802680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 812680Sktlim@umich.edu * state that might be needed by external objects, ranging from 822680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 832680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 842680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 852680Sktlim@umich.edu * 862680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 872680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 882680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 892682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 902680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 912680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 922680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 932680Sktlim@umich.edu */ 942680Sktlim@umich.educlass ThreadContext 952SN/A{ 962107SN/A protected: 972107SN/A typedef TheISA::MachInst MachInst; 989920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 9912109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10012109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 1012SN/A public: 1026029Ssteve.reinhardt@amd.com 103246SN/A enum Status 104246SN/A { 105246SN/A /// Running. Instructions should be executed only when 106246SN/A /// the context is in this state. 107246SN/A Active, 108246SN/A 109246SN/A /// Temporarily inactive. Entered while waiting for 1102190SN/A /// synchronization, etc. 111246SN/A Suspended, 112246SN/A 113246SN/A /// Permanently shut down. Entered when target executes 114246SN/A /// m5exit pseudo-instruction. When all contexts enter 115246SN/A /// this state, the simulation will terminate. 116246SN/A Halted 117246SN/A }; 1182SN/A 1192680Sktlim@umich.edu virtual ~ThreadContext() { }; 1202423SN/A 1212190SN/A virtual BaseCPU *getCpuPtr() = 0; 122180SN/A 12310110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1242190SN/A 12510190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 12610190Sakash.bagdia@arm.com 12710110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1285715Shsul@eecs.umich.edu 1295715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1305714Shsul@eecs.umich.edu 13110110Sandreas.hansson@arm.com virtual int contextId() const = 0; 1325714Shsul@eecs.umich.edu 1335714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1345714Shsul@eecs.umich.edu 13512406Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 1362190SN/A 13712406Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 1382521SN/A 1398887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1408733Sgeoffrey.blake@arm.com 1419020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1428541Sgblack@eecs.umich.edu 1434997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1444997Sgblack@eecs.umich.edu 1453548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1462654SN/A 1478852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1482521SN/A 1498852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1503673Srdreslin@umich.edu 1518706Sandreas.hansson@arm.com /** 1528706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1538706Sandreas.hansson@arm.com * the data port of the CPU. 1548706Sandreas.hansson@arm.com * 1558706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1568706Sandreas.hansson@arm.com */ 1578706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1588799Sgblack@eecs.umich.edu 1598852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1602518SN/A 1612190SN/A virtual Process *getProcessPtr() = 0; 1622190SN/A 16311886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 16411886Sbrandon.potter@amd.com 1652190SN/A virtual Status status() const = 0; 1662159SN/A 1672235SN/A virtual void setStatus(Status new_status) = 0; 1682103SN/A 16910407Smitch.hayenga@arm.com /// Set the status to Active. 17010407Smitch.hayenga@arm.com virtual void activate() = 0; 171393SN/A 172393SN/A /// Set the status to Suspended. 17310407Smitch.hayenga@arm.com virtual void suspend() = 0; 174393SN/A 175393SN/A /// Set the status to Halted. 17610407Smitch.hayenga@arm.com virtual void halt() = 0; 1772159SN/A 17811627Smichael.lebeane@amd.com /// Quiesce thread context 17911627Smichael.lebeane@amd.com void quiesce(); 18011627Smichael.lebeane@amd.com 18111627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 18211627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 18311627Smichael.lebeane@amd.com 1842190SN/A virtual void dumpFuncProfile() = 0; 1852159SN/A 1862680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1872159SN/A 1882190SN/A virtual void regStats(const std::string &name) = 0; 1892159SN/A 1902313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1912235SN/A 1922235SN/A // Not necessarily the best location for these... 1932235SN/A // Having an extra function just to read these is obnoxious 1942235SN/A virtual Tick readLastActivate() = 0; 1952235SN/A virtual Tick readLastSuspend() = 0; 1962254SN/A 1972254SN/A virtual void profileClear() = 0; 1982254SN/A virtual void profileSample() = 0; 1992235SN/A 2002680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2012159SN/A 2022190SN/A virtual void clearArchRegs() = 0; 2032159SN/A 2042159SN/A // 2052159SN/A // New accessors for new decoder. 2062159SN/A // 20713557Sgabeblack@google.com virtual RegVal readIntReg(int reg_idx) = 0; 2082159SN/A 20913557Sgabeblack@google.com virtual RegVal readFloatRegBits(int reg_idx) = 0; 2102159SN/A 21112109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 21212109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 21312109SRekai.GonzalezAlberquilla@arm.com 21412109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 21512109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 21612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 21712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 21812109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const = 0; 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 22212109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const = 0; 22312109SRekai.GonzalezAlberquilla@arm.com 22412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 22512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 22612109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const = 0; 22712109SRekai.GonzalezAlberquilla@arm.com 22812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 22912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 23012109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const = 0; 23112109SRekai.GonzalezAlberquilla@arm.com 23212109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 23312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 23512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 23712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 23912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 24112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 24412109SRekai.GonzalezAlberquilla@arm.com 2459920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) = 0; 2469920Syasuko.eckert@amd.com 24713557Sgabeblack@google.com virtual void setIntReg(int reg_idx, RegVal val) = 0; 2482159SN/A 24913557Sgabeblack@google.com virtual void setFloatRegBits(int reg_idx, RegVal val) = 0; 2502455SN/A 25112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 25212109SRekai.GonzalezAlberquilla@arm.com 25312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 25412109SRekai.GonzalezAlberquilla@arm.com 2559920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) = 0; 2569920Syasuko.eckert@amd.com 2577720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2582159SN/A 2597720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2602159SN/A 26111886Sbrandon.potter@amd.com void 26211886Sbrandon.potter@amd.com setNPC(Addr val) 26311886Sbrandon.potter@amd.com { 26411886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 26511886Sbrandon.potter@amd.com pc_state.setNPC(val); 26611886Sbrandon.potter@amd.com pcState(pc_state); 26711886Sbrandon.potter@amd.com } 26811886Sbrandon.potter@amd.com 2698733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2708733Sgeoffrey.blake@arm.com 2717720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2722159SN/A 2737720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2742159SN/A 2757720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2765260Sksewell@umich.edu 27713557Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0; 2784172Ssaidi@eecs.umich.edu 27913557Sgabeblack@google.com virtual RegVal readMiscReg(int misc_reg) = 0; 2802159SN/A 28113582Sgabeblack@google.com virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0; 2822190SN/A 28313582Sgabeblack@google.com virtual void setMiscReg(int misc_reg, RegVal val) = 0; 2842190SN/A 28512106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 2866313Sgblack@eecs.umich.edu 28713557Sgabeblack@google.com virtual RegVal 28812106SRekai.GonzalezAlberquilla@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 2896221Snate@binkert.org { 2906221Snate@binkert.org return 0; 2916221Snate@binkert.org } 2924661Sksewell@umich.edu 2936221Snate@binkert.org virtual void 29413582Sgabeblack@google.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 2956221Snate@binkert.org { 2966221Snate@binkert.org } 2974661Sksewell@umich.edu 2982235SN/A // Also not necessarily the best location for these two. Hopefully will go 2992235SN/A // away once we decide upon where st cond failures goes. 3002190SN/A virtual unsigned readStCondFailures() = 0; 3012190SN/A 3022190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 3032159SN/A 3042235SN/A // Same with st cond failures. 3052190SN/A virtual Counter readFuncExeInst() = 0; 3062834Sksewell@umich.edu 30711877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 3084111Sgblack@eecs.umich.edu 3092834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 3102834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 3112834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 3122834Sksewell@umich.edu virtual int exit() { return 1; }; 3132525SN/A 3145217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 3155217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 3169426SAndreas.Sandberg@ARM.com 3179426SAndreas.Sandberg@ARM.com /** @{ */ 3189426SAndreas.Sandberg@ARM.com /** 3199426SAndreas.Sandberg@ARM.com * Flat register interfaces 3209426SAndreas.Sandberg@ARM.com * 3219426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 3229426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 32312106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 3249426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 3259426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 3269426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 3279426SAndreas.Sandberg@ARM.com */ 3289426SAndreas.Sandberg@ARM.com 32913557Sgabeblack@google.com virtual RegVal readIntRegFlat(int idx) = 0; 33013557Sgabeblack@google.com virtual void setIntRegFlat(int idx, RegVal val) = 0; 3319426SAndreas.Sandberg@ARM.com 33213557Sgabeblack@google.com virtual RegVal readFloatRegBitsFlat(int idx) = 0; 33313557Sgabeblack@google.com virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0; 3349426SAndreas.Sandberg@ARM.com 33512109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; 33612109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; 33712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0; 33812109SRekai.GonzalezAlberquilla@arm.com 33912109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElemFlat(const RegIndex& idx, 34012109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIdx) const = 0; 34112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 34212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) = 0; 34312109SRekai.GonzalezAlberquilla@arm.com 3449920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx) = 0; 3459920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val) = 0; 3469426SAndreas.Sandberg@ARM.com /** @} */ 3479426SAndreas.Sandberg@ARM.com 3482159SN/A}; 3492159SN/A 3502682Sktlim@umich.edu/** 3512682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3522682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3532682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3542682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3552682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3562682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3572682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3582682Sktlim@umich.edu * simple_thread.hh for an example of this. 3592682Sktlim@umich.edu */ 3602680Sktlim@umich.edutemplate <class TC> 3612680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3622190SN/A{ 3632190SN/A public: 3642680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3652680Sktlim@umich.edu { actualTC = actual_tc; } 3662159SN/A 3672190SN/A private: 3682680Sktlim@umich.edu TC *actualTC; 3692SN/A 3702SN/A public: 3712SN/A 3722680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3732SN/A 37410110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 3752SN/A 37610190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 37710190Sakash.bagdia@arm.com 37810110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 3795715Shsul@eecs.umich.edu 38010110Sandreas.hansson@arm.com void setThreadId(int id) { actualTC->setThreadId(id); } 3815714Shsul@eecs.umich.edu 38210110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 3835714Shsul@eecs.umich.edu 3845714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3855714Shsul@eecs.umich.edu 38612406Sgabeblack@google.com BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 3871917SN/A 38812406Sgabeblack@google.com BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3892521SN/A 3908887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3918733Sgeoffrey.blake@arm.com 3929020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3938541Sgblack@eecs.umich.edu 3944997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3954997Sgblack@eecs.umich.edu 3963548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3973548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3982654SN/A 3998852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 4002521SN/A 4018852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 4023673Srdreslin@umich.edu 4038706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 4048799Sgblack@eecs.umich.edu 4058852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 4062518SN/A 4072680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 4082SN/A 40911886Sbrandon.potter@amd.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 41011886Sbrandon.potter@amd.com 4112680Sktlim@umich.edu Status status() const { return actualTC->status(); } 412595SN/A 4132680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 4142SN/A 41510407Smitch.hayenga@arm.com /// Set the status to Active. 41610407Smitch.hayenga@arm.com void activate() { actualTC->activate(); } 4172SN/A 4182190SN/A /// Set the status to Suspended. 41910407Smitch.hayenga@arm.com void suspend() { actualTC->suspend(); } 4202SN/A 4212190SN/A /// Set the status to Halted. 42210407Smitch.hayenga@arm.com void halt() { actualTC->halt(); } 423217SN/A 42411627Smichael.lebeane@amd.com /// Quiesce thread context 42511627Smichael.lebeane@amd.com void quiesce() { actualTC->quiesce(); } 42611627Smichael.lebeane@amd.com 42711627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 42811627Smichael.lebeane@amd.com void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 42911627Smichael.lebeane@amd.com 4302680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 4312190SN/A 4322680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 4332680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 4342190SN/A 4352680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 4362190SN/A 4372680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 4382235SN/A 4392680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 4402680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 4412254SN/A 4422680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 4432680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 4442SN/A 4452190SN/A // @todo: Do I need this? 4462680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 4472SN/A 4482680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 449716SN/A 4502SN/A // 4512SN/A // New accessors for new decoder. 4522SN/A // 45313557Sgabeblack@google.com RegVal readIntReg(int reg_idx) 4542680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 4552SN/A 45613557Sgabeblack@google.com RegVal readFloatRegBits(int reg_idx) 4572680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4582SN/A 45912109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(const RegId& reg) const 46012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecReg(reg); } 46112109SRekai.GonzalezAlberquilla@arm.com 46212109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(const RegId& reg) 46312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecReg(reg); } 46412109SRekai.GonzalezAlberquilla@arm.com 46512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 46612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 46712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 46812109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 46912109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 47012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec8BitLaneReg(reg); } 47112109SRekai.GonzalezAlberquilla@arm.com 47212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 47312109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 47412109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 47512109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec16BitLaneReg(reg); } 47612109SRekai.GonzalezAlberquilla@arm.com 47712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 47812109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 47912109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 48012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec32BitLaneReg(reg); } 48112109SRekai.GonzalezAlberquilla@arm.com 48212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 48312109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 48412109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 48512109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec64BitLaneReg(reg); } 48612109SRekai.GonzalezAlberquilla@arm.com 48712109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 48812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 48912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 49012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 49112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 49212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 49312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 49412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 49512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 49612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 49712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 49812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 49912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 50012109SRekai.GonzalezAlberquilla@arm.com /** @} */ 50112109SRekai.GonzalezAlberquilla@arm.com 50212109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 50312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElem(reg); } 50412109SRekai.GonzalezAlberquilla@arm.com 5059920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 5069920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 5079920Syasuko.eckert@amd.com 50813557Sgabeblack@google.com void setIntReg(int reg_idx, RegVal val) 5092680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 5102SN/A 51113557Sgabeblack@google.com void setFloatRegBits(int reg_idx, RegVal val) 5122680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 5132SN/A 51412109SRekai.GonzalezAlberquilla@arm.com void setVecReg(const RegId& reg, const VecRegContainer& val) 51512109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecReg(reg, val); } 51612109SRekai.GonzalezAlberquilla@arm.com 51712109SRekai.GonzalezAlberquilla@arm.com void setVecElem(const RegId& reg, const VecElem& val) 51812109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElem(reg, val); } 51912109SRekai.GonzalezAlberquilla@arm.com 5209920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 5219920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 5229920Syasuko.eckert@amd.com 5237720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 5242SN/A 5257720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 5262206SN/A 5278733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 5288733Sgeoffrey.blake@arm.com 5297720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 5307720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 5317720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 5325260Sksewell@umich.edu 5337597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 5347597Sminkyu.jeong@arm.com 5357597Sminkyu.jeong@arm.com void setPredicate(bool val) 5367597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 5377597Sminkyu.jeong@arm.com 53813557Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg) const 5394172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 5404172Ssaidi@eecs.umich.edu 54113557Sgabeblack@google.com RegVal readMiscReg(int misc_reg) 5422680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 5432SN/A 54413582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, RegVal val) 5454172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 5462SN/A 54713582Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val) 5482680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 5492SN/A 55012106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const 55112106SRekai.GonzalezAlberquilla@arm.com { return actualTC->flattenRegId(regId); } 55210033SAli.Saidi@ARM.com 5532190SN/A unsigned readStCondFailures() 5542680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 5552190SN/A 5562190SN/A void setStCondFailures(unsigned sc_failures) 5572680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 5582SN/A 55911877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 56011877Sbrandon.potter@amd.com { actualTC->syscall(callnum, fault); } 5614111Sgblack@eecs.umich.edu 5622680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 5639426SAndreas.Sandberg@ARM.com 56413557Sgabeblack@google.com RegVal readIntRegFlat(int idx) 5659426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 5669426SAndreas.Sandberg@ARM.com 56713557Sgabeblack@google.com void setIntRegFlat(int idx, RegVal val) 5689426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 5699426SAndreas.Sandberg@ARM.com 57013557Sgabeblack@google.com RegVal readFloatRegBitsFlat(int idx) 5719426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 5729426SAndreas.Sandberg@ARM.com 57313557Sgabeblack@google.com void setFloatRegBitsFlat(int idx, RegVal val) 5749426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 5759920Syasuko.eckert@amd.com 57612109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegFlat(int id) const 57712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecRegFlat(id); } 57812109SRekai.GonzalezAlberquilla@arm.com 57912109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegFlat(int id) 58012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecRegFlat(id); } 58112109SRekai.GonzalezAlberquilla@arm.com 58212109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(int idx, const VecRegContainer& val) 58312109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecRegFlat(idx, val); } 58412109SRekai.GonzalezAlberquilla@arm.com 58512109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& id, 58612109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 58712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElemFlat(id, elemIndex); } 58812109SRekai.GonzalezAlberquilla@arm.com 58912109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex, 59012109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) 59112109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElemFlat(id, elemIndex, val); } 59212109SRekai.GonzalezAlberquilla@arm.com 5939920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 5949920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 5959920Syasuko.eckert@amd.com 5969920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 5979920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 5982SN/A}; 5992SN/A 6009428SAndreas.Sandberg@ARM.com/** @{ */ 6019428SAndreas.Sandberg@ARM.com/** 6029428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 6039428SAndreas.Sandberg@ARM.com * 6049428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 6059428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 6069428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 6079428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 6089428SAndreas.Sandberg@ARM.com */ 6099428SAndreas.Sandberg@ARM.com 61010905Sandreas.sandberg@arm.comvoid serialize(ThreadContext &tc, CheckpointOut &cp); 61110905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 6129428SAndreas.Sandberg@ARM.com 6139428SAndreas.Sandberg@ARM.com/** @} */ 6149428SAndreas.Sandberg@ARM.com 6159441SAndreas.Sandberg@ARM.com 6169441SAndreas.Sandberg@ARM.com/** 6179441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 6189441SAndreas.Sandberg@ARM.com * 6199441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 6209441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 6219441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 6229441SAndreas.Sandberg@ARM.com * 6239441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 6249441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 6259441SAndreas.Sandberg@ARM.com */ 6269441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 6279441SAndreas.Sandberg@ARM.com 6282190SN/A#endif 629