thread_context.hh revision 13582 
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60    class Decoder;
61}
62class BaseCPU;
63class BaseTLB;
64class CheckerCPU;
65class Checkpoint;
66class EndQuiesceEvent;
67class SETranslatingPortProxy;
68class FSTranslatingPortProxy;
69class PortProxy;
70class Process;
71class System;
72namespace TheISA {
73    namespace Kernel {
74        class Statistics;
75    }
76}
77
78/**
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
85 *
86 * The ThreadContext is slightly different than the ExecContext.  The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems).  Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96  protected:
97    typedef TheISA::MachInst MachInst;
98    typedef TheISA::CCReg CCReg;
99    using VecRegContainer = TheISA::VecRegContainer;
100    using VecElem = TheISA::VecElem;
101  public:
102
103    enum Status
104    {
105        /// Running.  Instructions should be executed only when
106        /// the context is in this state.
107        Active,
108
109        /// Temporarily inactive.  Entered while waiting for
110        /// synchronization, etc.
111        Suspended,
112
113        /// Permanently shut down.  Entered when target executes
114        /// m5exit pseudo-instruction.  When all contexts enter
115        /// this state, the simulation will terminate.
116        Halted
117    };
118
119    virtual ~ThreadContext() { };
120
121    virtual BaseCPU *getCpuPtr() = 0;
122
123    virtual int cpuId() const = 0;
124
125    virtual uint32_t socketId() const = 0;
126
127    virtual int threadId() const = 0;
128
129    virtual void setThreadId(int id) = 0;
130
131    virtual int contextId() const = 0;
132
133    virtual void setContextId(int id) = 0;
134
135    virtual BaseTLB *getITBPtr() = 0;
136
137    virtual BaseTLB *getDTBPtr() = 0;
138
139    virtual CheckerCPU *getCheckerCpuPtr() = 0;
140
141    virtual TheISA::Decoder *getDecoderPtr() = 0;
142
143    virtual System *getSystemPtr() = 0;
144
145    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
146
147    virtual PortProxy &getPhysProxy() = 0;
148
149    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
150
151    /**
152     * Initialise the physical and virtual port proxies and tie them to
153     * the data port of the CPU.
154     *
155     * tc ThreadContext for the virtual-to-physical translation
156     */
157    virtual void initMemProxies(ThreadContext *tc) = 0;
158
159    virtual SETranslatingPortProxy &getMemProxy() = 0;
160
161    virtual Process *getProcessPtr() = 0;
162
163    virtual void setProcessPtr(Process *p) = 0;
164
165    virtual Status status() const = 0;
166
167    virtual void setStatus(Status new_status) = 0;
168
169    /// Set the status to Active.
170    virtual void activate() = 0;
171
172    /// Set the status to Suspended.
173    virtual void suspend() = 0;
174
175    /// Set the status to Halted.
176    virtual void halt() = 0;
177
178    /// Quiesce thread context
179    void quiesce();
180
181    /// Quiesce, suspend, and schedule activate at resume
182    void quiesceTick(Tick resume);
183
184    virtual void dumpFuncProfile() = 0;
185
186    virtual void takeOverFrom(ThreadContext *old_context) = 0;
187
188    virtual void regStats(const std::string &name) = 0;
189
190    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
191
192    // Not necessarily the best location for these...
193    // Having an extra function just to read these is obnoxious
194    virtual Tick readLastActivate() = 0;
195    virtual Tick readLastSuspend() = 0;
196
197    virtual void profileClear() = 0;
198    virtual void profileSample() = 0;
199
200    virtual void copyArchRegs(ThreadContext *tc) = 0;
201
202    virtual void clearArchRegs() = 0;
203
204    //
205    // New accessors for new decoder.
206    //
207    virtual RegVal readIntReg(int reg_idx) = 0;
208
209    virtual RegVal readFloatRegBits(int reg_idx) = 0;
210
211    virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
212    virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
213
214    /** Vector Register Lane Interfaces. */
215    /** @{ */
216    /** Reads source vector 8bit operand. */
217    virtual ConstVecLane8
218    readVec8BitLaneReg(const RegId& reg) const = 0;
219
220    /** Reads source vector 16bit operand. */
221    virtual ConstVecLane16
222    readVec16BitLaneReg(const RegId& reg) const = 0;
223
224    /** Reads source vector 32bit operand. */
225    virtual ConstVecLane32
226    readVec32BitLaneReg(const RegId& reg) const = 0;
227
228    /** Reads source vector 64bit operand. */
229    virtual ConstVecLane64
230    readVec64BitLaneReg(const RegId& reg) const = 0;
231
232    /** Write a lane of the destination vector register. */
233    virtual void setVecLane(const RegId& reg,
234            const LaneData<LaneSize::Byte>& val) = 0;
235    virtual void setVecLane(const RegId& reg,
236            const LaneData<LaneSize::TwoByte>& val) = 0;
237    virtual void setVecLane(const RegId& reg,
238            const LaneData<LaneSize::FourByte>& val) = 0;
239    virtual void setVecLane(const RegId& reg,
240            const LaneData<LaneSize::EightByte>& val) = 0;
241    /** @} */
242
243    virtual const VecElem& readVecElem(const RegId& reg) const = 0;
244
245    virtual CCReg readCCReg(int reg_idx) = 0;
246
247    virtual void setIntReg(int reg_idx, RegVal val) = 0;
248
249    virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
250
251    virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
252
253    virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
254
255    virtual void setCCReg(int reg_idx, CCReg val) = 0;
256
257    virtual TheISA::PCState pcState() = 0;
258
259    virtual void pcState(const TheISA::PCState &val) = 0;
260
261    void
262    setNPC(Addr val)
263    {
264        TheISA::PCState pc_state = pcState();
265        pc_state.setNPC(val);
266        pcState(pc_state);
267    }
268
269    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
270
271    virtual Addr instAddr() = 0;
272
273    virtual Addr nextInstAddr() = 0;
274
275    virtual MicroPC microPC() = 0;
276
277    virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
278
279    virtual RegVal readMiscReg(int misc_reg) = 0;
280
281    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
282
283    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
284
285    virtual RegId flattenRegId(const RegId& regId) const = 0;
286
287    virtual RegVal
288    readRegOtherThread(const RegId& misc_reg, ThreadID tid)
289    {
290        return 0;
291    }
292
293    virtual void
294    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
295    {
296    }
297
298    // Also not necessarily the best location for these two.  Hopefully will go
299    // away once we decide upon where st cond failures goes.
300    virtual unsigned readStCondFailures() = 0;
301
302    virtual void setStCondFailures(unsigned sc_failures) = 0;
303
304    // Same with st cond failures.
305    virtual Counter readFuncExeInst() = 0;
306
307    virtual void syscall(int64_t callnum, Fault *fault) = 0;
308
309    // This function exits the thread context in the CPU and returns
310    // 1 if the CPU has no more active threads (meaning it's OK to exit);
311    // Used in syscall-emulation mode when a  thread calls the exit syscall.
312    virtual int exit() { return 1; };
313
314    /** function to compare two thread contexts (for debugging) */
315    static void compare(ThreadContext *one, ThreadContext *two);
316
317    /** @{ */
318    /**
319     * Flat register interfaces
320     *
321     * Some architectures have different registers visible in
322     * different modes. Such architectures "flatten" a register (see
323     * flattenRegId()) to map it into the
324     * gem5 register file. This interface provides a flat interface to
325     * the underlying register file, which allows for example
326     * serialization code to access all registers.
327     */
328
329    virtual RegVal readIntRegFlat(int idx) = 0;
330    virtual void setIntRegFlat(int idx, RegVal val) = 0;
331
332    virtual RegVal readFloatRegBitsFlat(int idx) = 0;
333    virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0;
334
335    virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
336    virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
337    virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
338
339    virtual const VecElem& readVecElemFlat(const RegIndex& idx,
340                                           const ElemIndex& elemIdx) const = 0;
341    virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
342                                const VecElem& val) = 0;
343
344    virtual CCReg readCCRegFlat(int idx) = 0;
345    virtual void setCCRegFlat(int idx, CCReg val) = 0;
346    /** @} */
347
348};
349
350/**
351 * ProxyThreadContext class that provides a way to implement a
352 * ThreadContext without having to derive from it. ThreadContext is an
353 * abstract class, so anything that derives from it and uses its
354 * interface will pay the overhead of virtual function calls.  This
355 * class is created to enable a user-defined Thread object to be used
356 * wherever ThreadContexts are used, without paying the overhead of
357 * virtual function calls when it is used by itself.  See
358 * simple_thread.hh for an example of this.
359 */
360template <class TC>
361class ProxyThreadContext : public ThreadContext
362{
363  public:
364    ProxyThreadContext(TC *actual_tc)
365    { actualTC = actual_tc; }
366
367  private:
368    TC *actualTC;
369
370  public:
371
372    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
373
374    int cpuId() const { return actualTC->cpuId(); }
375
376    uint32_t socketId() const { return actualTC->socketId(); }
377
378    int threadId() const { return actualTC->threadId(); }
379
380    void setThreadId(int id) { actualTC->setThreadId(id); }
381
382    int contextId() const { return actualTC->contextId(); }
383
384    void setContextId(int id) { actualTC->setContextId(id); }
385
386    BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
387
388    BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
389
390    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
391
392    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
393
394    System *getSystemPtr() { return actualTC->getSystemPtr(); }
395
396    TheISA::Kernel::Statistics *getKernelStats()
397    { return actualTC->getKernelStats(); }
398
399    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
400
401    FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
402
403    void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
404
405    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
406
407    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
408
409    void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
410
411    Status status() const { return actualTC->status(); }
412
413    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
414
415    /// Set the status to Active.
416    void activate() { actualTC->activate(); }
417
418    /// Set the status to Suspended.
419    void suspend() { actualTC->suspend(); }
420
421    /// Set the status to Halted.
422    void halt() { actualTC->halt(); }
423
424    /// Quiesce thread context
425    void quiesce() { actualTC->quiesce(); }
426
427    /// Quiesce, suspend, and schedule activate at resume
428    void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
429
430    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
431
432    void takeOverFrom(ThreadContext *oldContext)
433    { actualTC->takeOverFrom(oldContext); }
434
435    void regStats(const std::string &name) { actualTC->regStats(name); }
436
437    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
438
439    Tick readLastActivate() { return actualTC->readLastActivate(); }
440    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
441
442    void profileClear() { return actualTC->profileClear(); }
443    void profileSample() { return actualTC->profileSample(); }
444
445    // @todo: Do I need this?
446    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
447
448    void clearArchRegs() { actualTC->clearArchRegs(); }
449
450    //
451    // New accessors for new decoder.
452    //
453    RegVal readIntReg(int reg_idx)
454    { return actualTC->readIntReg(reg_idx); }
455
456    RegVal readFloatRegBits(int reg_idx)
457    { return actualTC->readFloatRegBits(reg_idx); }
458
459    const VecRegContainer& readVecReg(const RegId& reg) const
460    { return actualTC->readVecReg(reg); }
461
462    VecRegContainer& getWritableVecReg(const RegId& reg)
463    { return actualTC->getWritableVecReg(reg); }
464
465    /** Vector Register Lane Interfaces. */
466    /** @{ */
467    /** Reads source vector 8bit operand. */
468    ConstVecLane8
469    readVec8BitLaneReg(const RegId& reg) const
470    { return actualTC->readVec8BitLaneReg(reg); }
471
472    /** Reads source vector 16bit operand. */
473    ConstVecLane16
474    readVec16BitLaneReg(const RegId& reg) const
475    { return actualTC->readVec16BitLaneReg(reg); }
476
477    /** Reads source vector 32bit operand. */
478    ConstVecLane32
479    readVec32BitLaneReg(const RegId& reg) const
480    { return actualTC->readVec32BitLaneReg(reg); }
481
482    /** Reads source vector 64bit operand. */
483    ConstVecLane64
484    readVec64BitLaneReg(const RegId& reg) const
485    { return actualTC->readVec64BitLaneReg(reg); }
486
487    /** Write a lane of the destination vector register. */
488    virtual void setVecLane(const RegId& reg,
489            const LaneData<LaneSize::Byte>& val)
490    { return actualTC->setVecLane(reg, val); }
491    virtual void setVecLane(const RegId& reg,
492            const LaneData<LaneSize::TwoByte>& val)
493    { return actualTC->setVecLane(reg, val); }
494    virtual void setVecLane(const RegId& reg,
495            const LaneData<LaneSize::FourByte>& val)
496    { return actualTC->setVecLane(reg, val); }
497    virtual void setVecLane(const RegId& reg,
498            const LaneData<LaneSize::EightByte>& val)
499    { return actualTC->setVecLane(reg, val); }
500    /** @} */
501
502    const VecElem& readVecElem(const RegId& reg) const
503    { return actualTC->readVecElem(reg); }
504
505    CCReg readCCReg(int reg_idx)
506    { return actualTC->readCCReg(reg_idx); }
507
508    void setIntReg(int reg_idx, RegVal val)
509    { actualTC->setIntReg(reg_idx, val); }
510
511    void setFloatRegBits(int reg_idx, RegVal val)
512    { actualTC->setFloatRegBits(reg_idx, val); }
513
514    void setVecReg(const RegId& reg, const VecRegContainer& val)
515    { actualTC->setVecReg(reg, val); }
516
517    void setVecElem(const RegId& reg, const VecElem& val)
518    { actualTC->setVecElem(reg, val); }
519
520    void setCCReg(int reg_idx, CCReg val)
521    { actualTC->setCCReg(reg_idx, val); }
522
523    TheISA::PCState pcState() { return actualTC->pcState(); }
524
525    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
526
527    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
528
529    Addr instAddr() { return actualTC->instAddr(); }
530    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
531    MicroPC microPC() { return actualTC->microPC(); }
532
533    bool readPredicate() { return actualTC->readPredicate(); }
534
535    void setPredicate(bool val)
536    { actualTC->setPredicate(val); }
537
538    RegVal readMiscRegNoEffect(int misc_reg) const
539    { return actualTC->readMiscRegNoEffect(misc_reg); }
540
541    RegVal readMiscReg(int misc_reg)
542    { return actualTC->readMiscReg(misc_reg); }
543
544    void setMiscRegNoEffect(int misc_reg, RegVal val)
545    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
546
547    void setMiscReg(int misc_reg, RegVal val)
548    { return actualTC->setMiscReg(misc_reg, val); }
549
550    RegId flattenRegId(const RegId& regId) const
551    { return actualTC->flattenRegId(regId); }
552
553    unsigned readStCondFailures()
554    { return actualTC->readStCondFailures(); }
555
556    void setStCondFailures(unsigned sc_failures)
557    { actualTC->setStCondFailures(sc_failures); }
558
559    void syscall(int64_t callnum, Fault *fault)
560    { actualTC->syscall(callnum, fault); }
561
562    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
563
564    RegVal readIntRegFlat(int idx)
565    { return actualTC->readIntRegFlat(idx); }
566
567    void setIntRegFlat(int idx, RegVal val)
568    { actualTC->setIntRegFlat(idx, val); }
569
570    RegVal readFloatRegBitsFlat(int idx)
571    { return actualTC->readFloatRegBitsFlat(idx); }
572
573    void setFloatRegBitsFlat(int idx, RegVal val)
574    { actualTC->setFloatRegBitsFlat(idx, val); }
575
576    const VecRegContainer& readVecRegFlat(int id) const
577    { return actualTC->readVecRegFlat(id); }
578
579    VecRegContainer& getWritableVecRegFlat(int id)
580    { return actualTC->getWritableVecRegFlat(id); }
581
582    void setVecRegFlat(int idx, const VecRegContainer& val)
583    { actualTC->setVecRegFlat(idx, val); }
584
585    const VecElem& readVecElemFlat(const RegIndex& id,
586                                   const ElemIndex& elemIndex) const
587    { return actualTC->readVecElemFlat(id, elemIndex); }
588
589    void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
590                        const VecElem& val)
591    { actualTC->setVecElemFlat(id, elemIndex, val); }
592
593    CCReg readCCRegFlat(int idx)
594    { return actualTC->readCCRegFlat(idx); }
595
596    void setCCRegFlat(int idx, CCReg val)
597    { actualTC->setCCRegFlat(idx, val); }
598};
599
600/** @{ */
601/**
602 * Thread context serialization helpers
603 *
604 * These helper functions provide a way to the data in a
605 * ThreadContext. They are provided as separate helper function since
606 * implementing them as members of the ThreadContext interface would
607 * be confusing when the ThreadContext is exported via a proxy.
608 */
609
610void serialize(ThreadContext &tc, CheckpointOut &cp);
611void unserialize(ThreadContext &tc, CheckpointIn &cp);
612
613/** @} */
614
615
616/**
617 * Copy state between thread contexts in preparation for CPU handover.
618 *
619 * @note This method modifies the old thread contexts as well as the
620 * new thread context. The old thread context will have its quiesce
621 * event descheduled if it is scheduled and its status set to halted.
622 *
623 * @param new_tc Destination ThreadContext.
624 * @param old_tc Source ThreadContext.
625 */
626void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
627
628#endif
629