thread_context.cc revision 13557:fc33e6048b25
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2012, 2016 ARM Limited 38703Sandreas.hansson@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48703Sandreas.hansson@arm.com * All rights reserved 58703Sandreas.hansson@arm.com * 68703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 141762SN/A * 157897Shestness@cs.utexas.edu * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu */ 432665Ssaidi@eecs.umich.edu 447897Shestness@cs.utexas.edu#include "cpu/thread_context.hh" 452SN/A 462SN/A#include "arch/kernel_stats.hh" 472SN/A#include "base/logging.hh" 482SN/A#include "base/trace.hh" 492SN/A#include "config/the_isa.hh" 502SN/A#include "cpu/base.hh" 5175SN/A#include "cpu/quiesce_event.hh" 522SN/A#include "debug/Context.hh" 532439SN/A#include "debug/Quiesce.hh" 542439SN/A#include "params/BaseCPU.hh" 55603SN/A#include "sim/full_system.hh" 56603SN/A 574762Snate@binkert.orgvoid 588769Sgblack@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 598852Sandreas.hansson@arm.com{ 608703Sandreas.hansson@arm.com DPRINTF(Context, "Comparing thread contexts\n"); 612520SN/A 624762Snate@binkert.org // First loop through the integer registers. 636658Snate@binkert.org for (int i = 0; i < TheISA::NumIntRegs; ++i) { 641634SN/A RegVal t1 = one->readIntReg(i); 658769Sgblack@eecs.umich.edu RegVal t2 = two->readIntReg(i); 668769Sgblack@eecs.umich.edu if (t1 != t2) 671634SN/A panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 682521SN/A i, t1, t2); 69803SN/A } 708769Sgblack@eecs.umich.edu 712SN/A // Then loop through the floating point registers. 728703Sandreas.hansson@arm.com for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 732SN/A RegVal t1 = one->readFloatRegBits(i); 748703Sandreas.hansson@arm.com RegVal t2 = two->readFloatRegBits(i); 758703Sandreas.hansson@arm.com if (t1 != t2) 768703Sandreas.hansson@arm.com panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 778703Sandreas.hansson@arm.com i, t1, t2); 788703Sandreas.hansson@arm.com } 798703Sandreas.hansson@arm.com 808703Sandreas.hansson@arm.com // Then loop through the vector registers. 818922Swilliam.wang@arm.com for (int i = 0; i < TheISA::NumVecRegs; ++i) { 828703Sandreas.hansson@arm.com RegId rid(VecRegClass, i); 838703Sandreas.hansson@arm.com const TheISA::VecRegContainer& t1 = one->readVecReg(rid); 848703Sandreas.hansson@arm.com const TheISA::VecRegContainer& t2 = two->readVecReg(rid); 858703Sandreas.hansson@arm.com if (t1 != t2) 868703Sandreas.hansson@arm.com panic("Vec reg idx %d doesn't match, one: %#x, two: %#x", 878703Sandreas.hansson@arm.com i, t1, t2); 888703Sandreas.hansson@arm.com } 898922Swilliam.wang@arm.com for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 908703Sandreas.hansson@arm.com RegVal t1 = one->readMiscRegNoEffect(i); 918703Sandreas.hansson@arm.com RegVal t2 = two->readMiscRegNoEffect(i); 928703Sandreas.hansson@arm.com if (t1 != t2) 938922Swilliam.wang@arm.com panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 948922Swilliam.wang@arm.com i, t1, t2); 958703Sandreas.hansson@arm.com } 968703Sandreas.hansson@arm.com 978703Sandreas.hansson@arm.com // loop through the Condition Code registers. 988703Sandreas.hansson@arm.com for (int i = 0; i < TheISA::NumCCRegs; ++i) { 998703Sandreas.hansson@arm.com TheISA::CCReg t1 = one->readCCReg(i); 1008703Sandreas.hansson@arm.com TheISA::CCReg t2 = two->readCCReg(i); 1018703Sandreas.hansson@arm.com if (t1 != t2) 1028703Sandreas.hansson@arm.com panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 103603SN/A i, t1, t2); 1042901Ssaidi@eecs.umich.edu } 1058703Sandreas.hansson@arm.com if (!(one->pcState() == two->pcState())) 1068706Sandreas.hansson@arm.com panic("PC state doesn't match."); 1078706Sandreas.hansson@arm.com int id1 = one->cpuId(); 1088706Sandreas.hansson@arm.com int id2 = two->cpuId(); 1098706Sandreas.hansson@arm.com if (id1 != id2) 1108706Sandreas.hansson@arm.com panic("CPU ids don't match, one: %d, two: %d", id1, id2); 1118706Sandreas.hansson@arm.com 1128852Sandreas.hansson@arm.com const ContextID cid1 = one->contextId(); 1138703Sandreas.hansson@arm.com const ContextID cid2 = two->contextId(); 1148703Sandreas.hansson@arm.com if (cid1 != cid2) 1158703Sandreas.hansson@arm.com panic("Context ids don't match, one: %d, two: %d", id1, id2); 1168703Sandreas.hansson@arm.com 1178852Sandreas.hansson@arm.com 1188703Sandreas.hansson@arm.com} 1198922Swilliam.wang@arm.com 1208703Sandreas.hansson@arm.comvoid 1218703Sandreas.hansson@arm.comThreadContext::quiesce() 1228703Sandreas.hansson@arm.com{ 1238703Sandreas.hansson@arm.com if (!getCpuPtr()->params()->do_quiesce) 1248922Swilliam.wang@arm.com return; 1258703Sandreas.hansson@arm.com 1262902Ssaidi@eecs.umich.edu DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name()); 1272902Ssaidi@eecs.umich.edu 1284762Snate@binkert.org suspend(); 1294762Snate@binkert.org if (getKernelStats()) 1304762Snate@binkert.org getKernelStats()->quiesce(); 1314762Snate@binkert.org} 1324762Snate@binkert.org 1334762Snate@binkert.org 1342901Ssaidi@eecs.umich.eduvoid 1352901Ssaidi@eecs.umich.eduThreadContext::quiesceTick(Tick resume) 1362901Ssaidi@eecs.umich.edu{ 1372901Ssaidi@eecs.umich.edu BaseCPU *cpu = getCpuPtr(); 1382901Ssaidi@eecs.umich.edu 1394762Snate@binkert.org if (!cpu->params()->do_quiesce) 1402901Ssaidi@eecs.umich.edu return; 1412521SN/A 1422SN/A EndQuiesceEvent *quiesceEvent = getQuiesceEvent(); 1432SN/A 1442680Sktlim@umich.edu cpu->reschedule(quiesceEvent, resume, true); 1455714Shsul@eecs.umich.edu 1461806SN/A DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume); 1476221Snate@binkert.org 1485713Shsul@eecs.umich.edu suspend(); 1495713Shsul@eecs.umich.edu if (getKernelStats()) 1505713Shsul@eecs.umich.edu getKernelStats()->quiesce(); 1515713Shsul@eecs.umich.edu} 1525714Shsul@eecs.umich.edu 1531806SN/Avoid 1546227Snate@binkert.orgserialize(ThreadContext &tc, CheckpointOut &cp) 1555714Shsul@eecs.umich.edu{ 1561806SN/A using namespace TheISA; 157180SN/A 1586029Ssteve.reinhardt@amd.com RegVal floatRegs[NumFloatRegs]; 1596029Ssteve.reinhardt@amd.com for (int i = 0; i < NumFloatRegs; ++i) 1606029Ssteve.reinhardt@amd.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 1616029Ssteve.reinhardt@amd.com // This is a bit ugly, but needed to maintain backwards 1628460SAli.Saidi@ARM.com // compatibility. 1638460SAli.Saidi@ARM.com arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1648460SAli.Saidi@ARM.com 1658460SAli.Saidi@ARM.com std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 1668460SAli.Saidi@ARM.com for (int i = 0; i < NumVecRegs; ++i) { 1678460SAli.Saidi@ARM.com vecRegs[i] = tc.readVecRegFlat(i); 1688460SAli.Saidi@ARM.com } 1698460SAli.Saidi@ARM.com SERIALIZE_CONTAINER(vecRegs); 1708765Sgblack@eecs.umich.edu 1718765Sgblack@eecs.umich.edu RegVal intRegs[NumIntRegs]; 1722378SN/A for (int i = 0; i < NumIntRegs; ++i) 1732378SN/A intRegs[i] = tc.readIntRegFlat(i); 1742520SN/A SERIALIZE_ARRAY(intRegs, NumIntRegs); 1752520SN/A 1768852Sandreas.hansson@arm.com#ifdef ISA_HAS_CC_REGS 1778852Sandreas.hansson@arm.com CCReg ccRegs[NumCCRegs]; 1782520SN/A for (int i = 0; i < NumCCRegs; ++i) 1791885SN/A ccRegs[i] = tc.readCCRegFlat(i); 1801070SN/A SERIALIZE_ARRAY(ccRegs, NumCCRegs); 181954SN/A#endif 1821070SN/A 1831070SN/A tc.pcState().serialize(cp); 1841070SN/A 1851070SN/A // thread_num and cpu_id are deterministic from the config 1861070SN/A} 1871070SN/A 1881070SN/Avoid 1891070SN/Aunserialize(ThreadContext &tc, CheckpointIn &cp) 1901070SN/A{ 1911070SN/A using namespace TheISA; 1921070SN/A 1931070SN/A RegVal floatRegs[NumFloatRegs]; 1947580SAli.Saidi@arm.com // This is a bit ugly, but needed to maintain backwards 1957580SAli.Saidi@arm.com // compatibility. 1967580SAli.Saidi@arm.com arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1977580SAli.Saidi@arm.com for (int i = 0; i < NumFloatRegs; ++i) 1987580SAli.Saidi@arm.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 1997580SAli.Saidi@arm.com 2007580SAli.Saidi@arm.com std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 2017580SAli.Saidi@arm.com UNSERIALIZE_CONTAINER(vecRegs); 2024997Sgblack@eecs.umich.edu for (int i = 0; i < NumVecRegs; ++i) { 2037770SAli.Saidi@ARM.com tc.setVecRegFlat(i, vecRegs[i]); 2044997Sgblack@eecs.umich.edu } 2054997Sgblack@eecs.umich.edu 2064997Sgblack@eecs.umich.edu RegVal intRegs[NumIntRegs]; 2074997Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 2087770SAli.Saidi@ARM.com for (int i = 0; i < NumIntRegs; ++i) 2094997Sgblack@eecs.umich.edu tc.setIntRegFlat(i, intRegs[i]); 2104997Sgblack@eecs.umich.edu 2115795Ssaidi@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 2125795Ssaidi@eecs.umich.edu CCReg ccRegs[NumCCRegs]; 2135795Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 2145795Ssaidi@eecs.umich.edu for (int i = 0; i < NumCCRegs; ++i) 2155795Ssaidi@eecs.umich.edu tc.setCCRegFlat(i, ccRegs[i]); 2165795Ssaidi@eecs.umich.edu#endif 2171885SN/A 2184762Snate@binkert.org PCState pcState; 2197914SBrad.Beckmann@amd.com pcState.unserialize(cp); 2207914SBrad.Beckmann@amd.com tc.pcState(pcState); 2218666SPrakash.Ramrakhyani@arm.com 2227914SBrad.Beckmann@amd.com // thread_num and cpu_id are deterministic from the config 2237914SBrad.Beckmann@amd.com} 2248832SAli.Saidi@ARM.com 2258832SAli.Saidi@ARM.comvoid 2268832SAli.Saidi@ARM.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 2278832SAli.Saidi@ARM.com{ 2288832SAli.Saidi@ARM.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 2298832SAli.Saidi@ARM.com 2308832SAli.Saidi@ARM.com ntc.setStatus(otc.status()); 2317914SBrad.Beckmann@amd.com ntc.copyArchRegs(&otc); 2328832SAli.Saidi@ARM.com ntc.setContextId(otc.contextId()); 2338832SAli.Saidi@ARM.com ntc.setThreadId(otc.threadId()); 2348832SAli.Saidi@ARM.com 2358832SAli.Saidi@ARM.com if (FullSystem) { 2368832SAli.Saidi@ARM.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 2378832SAli.Saidi@ARM.com 2388832SAli.Saidi@ARM.com BaseCPU *ncpu(ntc.getCpuPtr()); 2398832SAli.Saidi@ARM.com assert(ncpu); 2408832SAli.Saidi@ARM.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 2418832SAli.Saidi@ARM.com assert(oqe); 2428832SAli.Saidi@ARM.com assert(oqe->tc == &otc); 2438832SAli.Saidi@ARM.com 2448832SAli.Saidi@ARM.com BaseCPU *ocpu(otc.getCpuPtr()); 2458832SAli.Saidi@ARM.com assert(ocpu); 2468832SAli.Saidi@ARM.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 2478832SAli.Saidi@ARM.com assert(nqe); 2488832SAli.Saidi@ARM.com assert(nqe->tc == &ntc); 2498832SAli.Saidi@ARM.com 2508832SAli.Saidi@ARM.com if (oqe->scheduled()) { 2518832SAli.Saidi@ARM.com ncpu->schedule(nqe, oqe->when()); 2528832SAli.Saidi@ARM.com ocpu->deschedule(oqe); 2538666SPrakash.Ramrakhyani@arm.com } 2547914SBrad.Beckmann@amd.com } 2557914SBrad.Beckmann@amd.com 2567914SBrad.Beckmann@amd.com otc.setStatus(ThreadContext::Halted); 2577914SBrad.Beckmann@amd.com} 2588666SPrakash.Ramrakhyani@arm.com