thread_context.cc revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "base/misc.hh"
45#include "base/trace.hh"
46#include "config/the_isa.hh"
47#include "cpu/base.hh"
48#include "cpu/quiesce_event.hh"
49#include "cpu/thread_context.hh"
50#include "debug/Context.hh"
51#include "sim/full_system.hh"
52
53void
54ThreadContext::compare(ThreadContext *one, ThreadContext *two)
55{
56    DPRINTF(Context, "Comparing thread contexts\n");
57
58    // First loop through the integer registers.
59    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
60        TheISA::IntReg t1 = one->readIntReg(i);
61        TheISA::IntReg t2 = two->readIntReg(i);
62        if (t1 != t2)
63            panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
64                  i, t1, t2);
65    }
66
67    // Then loop through the floating point registers.
68    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
69        TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
70        TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
71        if (t1 != t2)
72            panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
73                  i, t1, t2);
74    }
75    for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
76        TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
77        TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
78        if (t1 != t2)
79            panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
80                  i, t1, t2);
81    }
82
83    // loop through the Condition Code registers.
84    for (int i = 0; i < TheISA::NumCCRegs; ++i) {
85        TheISA::CCReg t1 = one->readCCReg(i);
86        TheISA::CCReg t2 = two->readCCReg(i);
87        if (t1 != t2)
88            panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
89                  i, t1, t2);
90    }
91
92    // loop through the Vector registers.
93    for (int i = 0; i < TheISA::NumVectorRegs; ++i) {
94        const TheISA::VectorReg &t1 = one->readVectorReg(i);
95        const TheISA::VectorReg &t2 = two->readVectorReg(i);
96        if (t1 != t2)
97            panic("Vector reg idx %d doesn't match", i);
98    }
99
100    if (!(one->pcState() == two->pcState()))
101        panic("PC state doesn't match.");
102    int id1 = one->cpuId();
103    int id2 = two->cpuId();
104    if (id1 != id2)
105        panic("CPU ids don't match, one: %d, two: %d", id1, id2);
106
107    id1 = one->contextId();
108    id2 = two->contextId();
109    if (id1 != id2)
110        panic("Context ids don't match, one: %d, two: %d", id1, id2);
111
112
113}
114
115void
116serialize(ThreadContext &tc, CheckpointOut &cp)
117{
118    using namespace TheISA;
119
120    FloatRegBits floatRegs[NumFloatRegs];
121    for (int i = 0; i < NumFloatRegs; ++i)
122        floatRegs[i] = tc.readFloatRegBitsFlat(i);
123    // This is a bit ugly, but needed to maintain backwards
124    // compatibility.
125    arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
126
127    IntReg intRegs[NumIntRegs];
128    for (int i = 0; i < NumIntRegs; ++i)
129        intRegs[i] = tc.readIntRegFlat(i);
130    SERIALIZE_ARRAY(intRegs, NumIntRegs);
131
132#ifdef ISA_HAS_CC_REGS
133    CCReg ccRegs[NumCCRegs];
134    for (int i = 0; i < NumCCRegs; ++i)
135        ccRegs[i] = tc.readCCRegFlat(i);
136    SERIALIZE_ARRAY(ccRegs, NumCCRegs);
137#endif
138
139#ifdef ISA_HAS_VECTOR_REGS
140    VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements];
141    for (int i = 0; i < NumVectorRegs; ++i) {
142        const VectorReg &v = tc.readVectorRegFlat(i);
143        for (int j = 0; i < NumVectorRegElements; ++j)
144            vectorRegs[i * NumVectorRegElements + j] = v[j];
145    }
146    SERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements);
147#endif
148
149    tc.pcState().serialize(cp);
150
151    // thread_num and cpu_id are deterministic from the config
152}
153
154void
155unserialize(ThreadContext &tc, CheckpointIn &cp)
156{
157    using namespace TheISA;
158
159    FloatRegBits floatRegs[NumFloatRegs];
160    // This is a bit ugly, but needed to maintain backwards
161    // compatibility.
162    arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
163    for (int i = 0; i < NumFloatRegs; ++i)
164        tc.setFloatRegBitsFlat(i, floatRegs[i]);
165
166    IntReg intRegs[NumIntRegs];
167    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
168    for (int i = 0; i < NumIntRegs; ++i)
169        tc.setIntRegFlat(i, intRegs[i]);
170
171#ifdef ISA_HAS_CC_REGS
172    CCReg ccRegs[NumCCRegs];
173    UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
174    for (int i = 0; i < NumCCRegs; ++i)
175        tc.setCCRegFlat(i, ccRegs[i]);
176#endif
177
178#ifdef ISA_HAS_VECTOR_REGS
179    VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements];
180    UNSERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements);
181    for (int i = 0; i < NumVectorRegs; ++i) {
182        VectorReg v;
183        for (int j = 0; i < NumVectorRegElements; ++j)
184            v[j] = vectorRegs[i * NumVectorRegElements + j];
185        tc.setVectorRegFlat(i, v);
186    }
187#endif
188
189    PCState pcState;
190    pcState.unserialize(cp);
191    tc.pcState(pcState);
192
193    // thread_num and cpu_id are deterministic from the config
194}
195
196void
197takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
198{
199    assert(ntc.getProcessPtr() == otc.getProcessPtr());
200
201    ntc.setStatus(otc.status());
202    ntc.copyArchRegs(&otc);
203    ntc.setContextId(otc.contextId());
204    ntc.setThreadId(otc.threadId());
205
206    if (FullSystem) {
207        assert(ntc.getSystemPtr() == otc.getSystemPtr());
208
209        BaseCPU *ncpu(ntc.getCpuPtr());
210        assert(ncpu);
211        EndQuiesceEvent *oqe(otc.getQuiesceEvent());
212        assert(oqe);
213        assert(oqe->tc == &otc);
214
215        BaseCPU *ocpu(otc.getCpuPtr());
216        assert(ocpu);
217        EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
218        assert(nqe);
219        assert(nqe->tc == &ntc);
220
221        if (oqe->scheduled()) {
222            ncpu->schedule(nqe, oqe->when());
223            ocpu->deschedule(oqe);
224        }
225    }
226
227    otc.setStatus(ThreadContext::Halted);
228}
229