thread_context.cc revision 9441
15217Ssaidi@eecs.umich.edu/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39428SAndreas.Sandberg@ARM.com * All rights reserved 49428SAndreas.Sandberg@ARM.com * 59428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139428SAndreas.Sandberg@ARM.com * 145217Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 155217Ssaidi@eecs.umich.edu * All rights reserved. 165217Ssaidi@eecs.umich.edu * 175217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 185217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 195217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 205217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 215217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 225217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 235217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 245217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 255217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 275217Ssaidi@eecs.umich.edu * 285217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395217Ssaidi@eecs.umich.edu * 405217Ssaidi@eecs.umich.edu * Authors: Kevin Lim 415217Ssaidi@eecs.umich.edu */ 425217Ssaidi@eecs.umich.edu 435217Ssaidi@eecs.umich.edu#include "base/misc.hh" 445217Ssaidi@eecs.umich.edu#include "base/trace.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 469441SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 479441SAndreas.Sandberg@ARM.com#include "cpu/quiesce_event.hh" 485217Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 498232Snate@binkert.org#include "debug/Context.hh" 509441SAndreas.Sandberg@ARM.com#include "sim/full_system.hh" 515217Ssaidi@eecs.umich.edu 525217Ssaidi@eecs.umich.eduvoid 535217Ssaidi@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 545217Ssaidi@eecs.umich.edu{ 555217Ssaidi@eecs.umich.edu DPRINTF(Context, "Comparing thread contexts\n"); 565217Ssaidi@eecs.umich.edu 575217Ssaidi@eecs.umich.edu // First loop through the integer registers. 585217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 595217Ssaidi@eecs.umich.edu TheISA::IntReg t1 = one->readIntReg(i); 605217Ssaidi@eecs.umich.edu TheISA::IntReg t2 = two->readIntReg(i); 615217Ssaidi@eecs.umich.edu if (t1 != t2) 625217Ssaidi@eecs.umich.edu panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 635217Ssaidi@eecs.umich.edu i, t1, t2); 645217Ssaidi@eecs.umich.edu } 655217Ssaidi@eecs.umich.edu 665217Ssaidi@eecs.umich.edu // Then loop through the floating point registers. 675217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 685217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 695217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 705217Ssaidi@eecs.umich.edu if (t1 != t2) 715217Ssaidi@eecs.umich.edu panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 725217Ssaidi@eecs.umich.edu i, t1, t2); 735217Ssaidi@eecs.umich.edu } 745217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 755217Ssaidi@eecs.umich.edu TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 765217Ssaidi@eecs.umich.edu TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 775217Ssaidi@eecs.umich.edu if (t1 != t2) 785217Ssaidi@eecs.umich.edu panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 795217Ssaidi@eecs.umich.edu i, t1, t2); 805217Ssaidi@eecs.umich.edu } 815217Ssaidi@eecs.umich.edu 827720Sgblack@eecs.umich.edu if (!(one->pcState() == two->pcState())) 837720Sgblack@eecs.umich.edu panic("PC state doesn't match."); 845712Shsul@eecs.umich.edu int id1 = one->cpuId(); 855712Shsul@eecs.umich.edu int id2 = two->cpuId(); 865217Ssaidi@eecs.umich.edu if (id1 != id2) 875217Ssaidi@eecs.umich.edu panic("CPU ids don't match, one: %d, two: %d", id1, id2); 885714Shsul@eecs.umich.edu 895714Shsul@eecs.umich.edu id1 = one->contextId(); 905714Shsul@eecs.umich.edu id2 = two->contextId(); 915714Shsul@eecs.umich.edu if (id1 != id2) 925714Shsul@eecs.umich.edu panic("Context ids don't match, one: %d, two: %d", id1, id2); 935714Shsul@eecs.umich.edu 945714Shsul@eecs.umich.edu 955217Ssaidi@eecs.umich.edu} 969428SAndreas.Sandberg@ARM.com 979428SAndreas.Sandberg@ARM.comvoid 989428SAndreas.Sandberg@ARM.comserialize(ThreadContext &tc, std::ostream &os) 999428SAndreas.Sandberg@ARM.com{ 1009428SAndreas.Sandberg@ARM.com using namespace TheISA; 1019428SAndreas.Sandberg@ARM.com 1029428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1039428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1049428SAndreas.Sandberg@ARM.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 1059428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1069428SAndreas.Sandberg@ARM.com // compatibility. 1079428SAndreas.Sandberg@ARM.com arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs); 1089428SAndreas.Sandberg@ARM.com 1099428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1109428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1119428SAndreas.Sandberg@ARM.com intRegs[i] = tc.readIntRegFlat(i); 1129428SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 1139428SAndreas.Sandberg@ARM.com 1149428SAndreas.Sandberg@ARM.com tc.pcState().serialize(os); 1159428SAndreas.Sandberg@ARM.com 1169428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 1179428SAndreas.Sandberg@ARM.com} 1189428SAndreas.Sandberg@ARM.com 1199428SAndreas.Sandberg@ARM.comvoid 1209428SAndreas.Sandberg@ARM.comunserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion) 1219428SAndreas.Sandberg@ARM.com{ 1229428SAndreas.Sandberg@ARM.com using namespace TheISA; 1239428SAndreas.Sandberg@ARM.com 1249428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1259428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1269428SAndreas.Sandberg@ARM.com // compatibility. 1279428SAndreas.Sandberg@ARM.com arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs); 1289428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1299428SAndreas.Sandberg@ARM.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 1309428SAndreas.Sandberg@ARM.com 1319428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1329428SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 1339428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1349428SAndreas.Sandberg@ARM.com tc.setIntRegFlat(i, intRegs[i]); 1359428SAndreas.Sandberg@ARM.com 1369428SAndreas.Sandberg@ARM.com PCState pcState; 1379428SAndreas.Sandberg@ARM.com pcState.unserialize(cp, section); 1389428SAndreas.Sandberg@ARM.com tc.pcState(pcState); 1399428SAndreas.Sandberg@ARM.com 1409428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 1419428SAndreas.Sandberg@ARM.com} 1429441SAndreas.Sandberg@ARM.com 1439441SAndreas.Sandberg@ARM.comvoid 1449441SAndreas.Sandberg@ARM.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 1459441SAndreas.Sandberg@ARM.com{ 1469441SAndreas.Sandberg@ARM.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 1479441SAndreas.Sandberg@ARM.com 1489441SAndreas.Sandberg@ARM.com ntc.setStatus(otc.status()); 1499441SAndreas.Sandberg@ARM.com ntc.copyArchRegs(&otc); 1509441SAndreas.Sandberg@ARM.com ntc.setContextId(otc.contextId()); 1519441SAndreas.Sandberg@ARM.com ntc.setThreadId(otc.threadId()); 1529441SAndreas.Sandberg@ARM.com 1539441SAndreas.Sandberg@ARM.com if (FullSystem) { 1549441SAndreas.Sandberg@ARM.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 1559441SAndreas.Sandberg@ARM.com 1569441SAndreas.Sandberg@ARM.com BaseCPU *ncpu(ntc.getCpuPtr()); 1579441SAndreas.Sandberg@ARM.com assert(ncpu); 1589441SAndreas.Sandberg@ARM.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 1599441SAndreas.Sandberg@ARM.com assert(oqe); 1609441SAndreas.Sandberg@ARM.com assert(oqe->tc == &otc); 1619441SAndreas.Sandberg@ARM.com 1629441SAndreas.Sandberg@ARM.com BaseCPU *ocpu(otc.getCpuPtr()); 1639441SAndreas.Sandberg@ARM.com assert(ocpu); 1649441SAndreas.Sandberg@ARM.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 1659441SAndreas.Sandberg@ARM.com assert(nqe); 1669441SAndreas.Sandberg@ARM.com assert(nqe->tc == &ntc); 1679441SAndreas.Sandberg@ARM.com 1689441SAndreas.Sandberg@ARM.com if (oqe->scheduled()) { 1699441SAndreas.Sandberg@ARM.com ncpu->schedule(nqe, oqe->when()); 1709441SAndreas.Sandberg@ARM.com ocpu->deschedule(oqe); 1719441SAndreas.Sandberg@ARM.com } 1729441SAndreas.Sandberg@ARM.com } 1739441SAndreas.Sandberg@ARM.com 1749441SAndreas.Sandberg@ARM.com otc.setStatus(ThreadContext::Halted); 1759441SAndreas.Sandberg@ARM.com} 176