thread_context.cc revision 9428 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/misc.hh"
44#include "base/trace.hh"
45#include "config/the_isa.hh"
46#include "cpu/thread_context.hh"
47#include "debug/Context.hh"
48
49void
50ThreadContext::compare(ThreadContext *one, ThreadContext *two)
51{
52    DPRINTF(Context, "Comparing thread contexts\n");
53
54    // First loop through the integer registers.
55    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
56        TheISA::IntReg t1 = one->readIntReg(i);
57        TheISA::IntReg t2 = two->readIntReg(i);
58        if (t1 != t2)
59            panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
60                  i, t1, t2);
61    }
62
63    // Then loop through the floating point registers.
64    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
65        TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
66        TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
67        if (t1 != t2)
68            panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
69                  i, t1, t2);
70    }
71    for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
72        TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
73        TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
74        if (t1 != t2)
75            panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
76                  i, t1, t2);
77    }
78
79    if (!(one->pcState() == two->pcState()))
80        panic("PC state doesn't match.");
81    int id1 = one->cpuId();
82    int id2 = two->cpuId();
83    if (id1 != id2)
84        panic("CPU ids don't match, one: %d, two: %d", id1, id2);
85
86    id1 = one->contextId();
87    id2 = two->contextId();
88    if (id1 != id2)
89        panic("Context ids don't match, one: %d, two: %d", id1, id2);
90
91
92}
93
94void
95serialize(ThreadContext &tc, std::ostream &os)
96{
97    using namespace TheISA;
98
99    FloatRegBits floatRegs[NumFloatRegs];
100    for (int i = 0; i < NumFloatRegs; ++i)
101        floatRegs[i] = tc.readFloatRegBitsFlat(i);
102    // This is a bit ugly, but needed to maintain backwards
103    // compatibility.
104    arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
105
106    IntReg intRegs[NumIntRegs];
107    for (int i = 0; i < NumIntRegs; ++i)
108        intRegs[i] = tc.readIntRegFlat(i);
109    SERIALIZE_ARRAY(intRegs, NumIntRegs);
110
111    tc.pcState().serialize(os);
112
113    // thread_num and cpu_id are deterministic from the config
114}
115
116void
117unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
118{
119    using namespace TheISA;
120
121    FloatRegBits floatRegs[NumFloatRegs];
122    // This is a bit ugly, but needed to maintain backwards
123    // compatibility.
124    arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
125    for (int i = 0; i < NumFloatRegs; ++i)
126        tc.setFloatRegBitsFlat(i, floatRegs[i]);
127
128    IntReg intRegs[NumIntRegs];
129    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
130    for (int i = 0; i < NumIntRegs; ++i)
131        tc.setIntRegFlat(i, intRegs[i]);
132
133    PCState pcState;
134    pcState.unserialize(cp, section);
135    tc.pcState(pcState);
136
137    // thread_num and cpu_id are deterministic from the config
138}
139