thread_context.cc revision 6658
110396Sakash.bagdia@arm.com/* 210396Sakash.bagdia@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 310396Sakash.bagdia@arm.com * All rights reserved. 410396Sakash.bagdia@arm.com * 510396Sakash.bagdia@arm.com * Redistribution and use in source and binary forms, with or without 610396Sakash.bagdia@arm.com * modification, are permitted provided that the following conditions are 710396Sakash.bagdia@arm.com * met: redistributions of source code must retain the above copyright 810396Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer; 910396Sakash.bagdia@arm.com * redistributions in binary form must reproduce the above copyright 1010396Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer in the 1110396Sakash.bagdia@arm.com * documentation and/or other materials provided with the distribution; 1210396Sakash.bagdia@arm.com * neither the name of the copyright holders nor the names of its 1310396Sakash.bagdia@arm.com * contributors may be used to endorse or promote products derived from 1410396Sakash.bagdia@arm.com * this software without specific prior written permission. 1510396Sakash.bagdia@arm.com * 1610396Sakash.bagdia@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710396Sakash.bagdia@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810396Sakash.bagdia@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910396Sakash.bagdia@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010396Sakash.bagdia@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110396Sakash.bagdia@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210396Sakash.bagdia@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310396Sakash.bagdia@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410396Sakash.bagdia@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510396Sakash.bagdia@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610396Sakash.bagdia@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710396Sakash.bagdia@arm.com * 2810396Sakash.bagdia@arm.com * Authors: Kevin Lim 2910396Sakash.bagdia@arm.com */ 3010396Sakash.bagdia@arm.com 3110396Sakash.bagdia@arm.com#include "base/misc.hh" 3210396Sakash.bagdia@arm.com#include "base/trace.hh" 3310396Sakash.bagdia@arm.com#include "config/the_isa.hh" 3410396Sakash.bagdia@arm.com#include "cpu/thread_context.hh" 3510396Sakash.bagdia@arm.com 3610396Sakash.bagdia@arm.comvoid 3710396Sakash.bagdia@arm.comThreadContext::compare(ThreadContext *one, ThreadContext *two) 3810396Sakash.bagdia@arm.com{ 3910396Sakash.bagdia@arm.com DPRINTF(Context, "Comparing thread contexts\n"); 4010396Sakash.bagdia@arm.com 4110396Sakash.bagdia@arm.com // First loop through the integer registers. 4210396Sakash.bagdia@arm.com for (int i = 0; i < TheISA::NumIntRegs; ++i) { 4310396Sakash.bagdia@arm.com TheISA::IntReg t1 = one->readIntReg(i); 4410396Sakash.bagdia@arm.com TheISA::IntReg t2 = two->readIntReg(i); 4510396Sakash.bagdia@arm.com if (t1 != t2) 4610396Sakash.bagdia@arm.com panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 4710396Sakash.bagdia@arm.com i, t1, t2); 4810396Sakash.bagdia@arm.com } 4910396Sakash.bagdia@arm.com 5010396Sakash.bagdia@arm.com // Then loop through the floating point registers. 5110396Sakash.bagdia@arm.com for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 5210396Sakash.bagdia@arm.com TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 5310396Sakash.bagdia@arm.com TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 5410396Sakash.bagdia@arm.com if (t1 != t2) 5510396Sakash.bagdia@arm.com panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 5610396Sakash.bagdia@arm.com i, t1, t2); 5710396Sakash.bagdia@arm.com } 5810396Sakash.bagdia@arm.com#if FULL_SYSTEM 5910396Sakash.bagdia@arm.com for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 6010396Sakash.bagdia@arm.com TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 6110396Sakash.bagdia@arm.com TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 6210396Sakash.bagdia@arm.com if (t1 != t2) 6310396Sakash.bagdia@arm.com panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 6410396Sakash.bagdia@arm.com i, t1, t2); 6510396Sakash.bagdia@arm.com } 6610396Sakash.bagdia@arm.com#endif 6710396Sakash.bagdia@arm.com 6810396Sakash.bagdia@arm.com Addr pc1 = one->readPC(); 6910396Sakash.bagdia@arm.com Addr pc2 = two->readPC(); 7010396Sakash.bagdia@arm.com if (pc1 != pc2) 7110396Sakash.bagdia@arm.com panic("PCs doesn't match, one: %#x, two: %#x", pc1, pc2); 7210396Sakash.bagdia@arm.com 7310396Sakash.bagdia@arm.com Addr npc1 = one->readNextPC(); 7410396Sakash.bagdia@arm.com Addr npc2 = two->readNextPC(); 7510396Sakash.bagdia@arm.com if (npc1 != npc2) 7610396Sakash.bagdia@arm.com panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2); 7710396Sakash.bagdia@arm.com 7810396Sakash.bagdia@arm.com int id1 = one->cpuId(); 7910396Sakash.bagdia@arm.com int id2 = two->cpuId(); 8010396Sakash.bagdia@arm.com if (id1 != id2) 8110396Sakash.bagdia@arm.com panic("CPU ids don't match, one: %d, two: %d", id1, id2); 8210396Sakash.bagdia@arm.com 8310396Sakash.bagdia@arm.com id1 = one->contextId(); 8410396Sakash.bagdia@arm.com id2 = two->contextId(); 8510396Sakash.bagdia@arm.com if (id1 != id2) 8610396Sakash.bagdia@arm.com panic("Context ids don't match, one: %d, two: %d", id1, id2); 8710396Sakash.bagdia@arm.com 8810396Sakash.bagdia@arm.com 8910396Sakash.bagdia@arm.com} 9010396Sakash.bagdia@arm.com