thread_context.cc revision 11627
15217Ssaidi@eecs.umich.edu/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49428SAndreas.Sandberg@ARM.com * All rights reserved 59428SAndreas.Sandberg@ARM.com * 69428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 149428SAndreas.Sandberg@ARM.com * 155217Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 165217Ssaidi@eecs.umich.edu * All rights reserved. 175217Ssaidi@eecs.umich.edu * 185217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu * 295217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu * 415217Ssaidi@eecs.umich.edu * Authors: Kevin Lim 425217Ssaidi@eecs.umich.edu */ 435217Ssaidi@eecs.umich.edu 4411627Smichael.lebeane@amd.com#include "arch/kernel_stats.hh" 455217Ssaidi@eecs.umich.edu#include "base/misc.hh" 465217Ssaidi@eecs.umich.edu#include "base/trace.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 489441SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 499441SAndreas.Sandberg@ARM.com#include "cpu/quiesce_event.hh" 505217Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 518232Snate@binkert.org#include "debug/Context.hh" 5211627Smichael.lebeane@amd.com#include "debug/Quiesce.hh" 5311627Smichael.lebeane@amd.com#include "params/BaseCPU.hh" 549441SAndreas.Sandberg@ARM.com#include "sim/full_system.hh" 555217Ssaidi@eecs.umich.edu 565217Ssaidi@eecs.umich.eduvoid 575217Ssaidi@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 585217Ssaidi@eecs.umich.edu{ 595217Ssaidi@eecs.umich.edu DPRINTF(Context, "Comparing thread contexts\n"); 605217Ssaidi@eecs.umich.edu 615217Ssaidi@eecs.umich.edu // First loop through the integer registers. 625217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 635217Ssaidi@eecs.umich.edu TheISA::IntReg t1 = one->readIntReg(i); 645217Ssaidi@eecs.umich.edu TheISA::IntReg t2 = two->readIntReg(i); 655217Ssaidi@eecs.umich.edu if (t1 != t2) 665217Ssaidi@eecs.umich.edu panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 675217Ssaidi@eecs.umich.edu i, t1, t2); 685217Ssaidi@eecs.umich.edu } 695217Ssaidi@eecs.umich.edu 705217Ssaidi@eecs.umich.edu // Then loop through the floating point registers. 715217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 725217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 735217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 745217Ssaidi@eecs.umich.edu if (t1 != t2) 755217Ssaidi@eecs.umich.edu panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 765217Ssaidi@eecs.umich.edu i, t1, t2); 775217Ssaidi@eecs.umich.edu } 785217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 795217Ssaidi@eecs.umich.edu TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 805217Ssaidi@eecs.umich.edu TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 815217Ssaidi@eecs.umich.edu if (t1 != t2) 825217Ssaidi@eecs.umich.edu panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 835217Ssaidi@eecs.umich.edu i, t1, t2); 845217Ssaidi@eecs.umich.edu } 855217Ssaidi@eecs.umich.edu 869920Syasuko.eckert@amd.com // loop through the Condition Code registers. 879920Syasuko.eckert@amd.com for (int i = 0; i < TheISA::NumCCRegs; ++i) { 889920Syasuko.eckert@amd.com TheISA::CCReg t1 = one->readCCReg(i); 899920Syasuko.eckert@amd.com TheISA::CCReg t2 = two->readCCReg(i); 909920Syasuko.eckert@amd.com if (t1 != t2) 919920Syasuko.eckert@amd.com panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 929920Syasuko.eckert@amd.com i, t1, t2); 939920Syasuko.eckert@amd.com } 947720Sgblack@eecs.umich.edu if (!(one->pcState() == two->pcState())) 957720Sgblack@eecs.umich.edu panic("PC state doesn't match."); 965712Shsul@eecs.umich.edu int id1 = one->cpuId(); 975712Shsul@eecs.umich.edu int id2 = two->cpuId(); 985217Ssaidi@eecs.umich.edu if (id1 != id2) 995217Ssaidi@eecs.umich.edu panic("CPU ids don't match, one: %d, two: %d", id1, id2); 1005714Shsul@eecs.umich.edu 10111005Sandreas.sandberg@arm.com const ContextID cid1 = one->contextId(); 10211005Sandreas.sandberg@arm.com const ContextID cid2 = two->contextId(); 10311005Sandreas.sandberg@arm.com if (cid1 != cid2) 1045714Shsul@eecs.umich.edu panic("Context ids don't match, one: %d, two: %d", id1, id2); 1055714Shsul@eecs.umich.edu 1065714Shsul@eecs.umich.edu 1075217Ssaidi@eecs.umich.edu} 1089428SAndreas.Sandberg@ARM.com 1099428SAndreas.Sandberg@ARM.comvoid 11011627Smichael.lebeane@amd.comThreadContext::quiesce() 11111627Smichael.lebeane@amd.com{ 11211627Smichael.lebeane@amd.com if (!getCpuPtr()->params()->do_quiesce) 11311627Smichael.lebeane@amd.com return; 11411627Smichael.lebeane@amd.com 11511627Smichael.lebeane@amd.com DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name()); 11611627Smichael.lebeane@amd.com 11711627Smichael.lebeane@amd.com suspend(); 11811627Smichael.lebeane@amd.com if (getKernelStats()) 11911627Smichael.lebeane@amd.com getKernelStats()->quiesce(); 12011627Smichael.lebeane@amd.com} 12111627Smichael.lebeane@amd.com 12211627Smichael.lebeane@amd.com 12311627Smichael.lebeane@amd.comvoid 12411627Smichael.lebeane@amd.comThreadContext::quiesceTick(Tick resume) 12511627Smichael.lebeane@amd.com{ 12611627Smichael.lebeane@amd.com BaseCPU *cpu = getCpuPtr(); 12711627Smichael.lebeane@amd.com 12811627Smichael.lebeane@amd.com if (!cpu->params()->do_quiesce) 12911627Smichael.lebeane@amd.com return; 13011627Smichael.lebeane@amd.com 13111627Smichael.lebeane@amd.com EndQuiesceEvent *quiesceEvent = getQuiesceEvent(); 13211627Smichael.lebeane@amd.com 13311627Smichael.lebeane@amd.com cpu->reschedule(quiesceEvent, resume, true); 13411627Smichael.lebeane@amd.com 13511627Smichael.lebeane@amd.com DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume); 13611627Smichael.lebeane@amd.com 13711627Smichael.lebeane@amd.com suspend(); 13811627Smichael.lebeane@amd.com if (getKernelStats()) 13911627Smichael.lebeane@amd.com getKernelStats()->quiesce(); 14011627Smichael.lebeane@amd.com} 14111627Smichael.lebeane@amd.com 14211627Smichael.lebeane@amd.comvoid 14310905Sandreas.sandberg@arm.comserialize(ThreadContext &tc, CheckpointOut &cp) 1449428SAndreas.Sandberg@ARM.com{ 1459428SAndreas.Sandberg@ARM.com using namespace TheISA; 1469428SAndreas.Sandberg@ARM.com 1479428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1489428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1499428SAndreas.Sandberg@ARM.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 1509428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1519428SAndreas.Sandberg@ARM.com // compatibility. 15210905Sandreas.sandberg@arm.com arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1539428SAndreas.Sandberg@ARM.com 1549428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1559428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1569428SAndreas.Sandberg@ARM.com intRegs[i] = tc.readIntRegFlat(i); 1579428SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 1589428SAndreas.Sandberg@ARM.com 1599920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1609920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 1619920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 1629920Syasuko.eckert@amd.com ccRegs[i] = tc.readCCRegFlat(i); 1639920Syasuko.eckert@amd.com SERIALIZE_ARRAY(ccRegs, NumCCRegs); 1649920Syasuko.eckert@amd.com#endif 1659920Syasuko.eckert@amd.com 16610905Sandreas.sandberg@arm.com tc.pcState().serialize(cp); 1679428SAndreas.Sandberg@ARM.com 1689428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 1699428SAndreas.Sandberg@ARM.com} 1709428SAndreas.Sandberg@ARM.com 1719428SAndreas.Sandberg@ARM.comvoid 17210905Sandreas.sandberg@arm.comunserialize(ThreadContext &tc, CheckpointIn &cp) 1739428SAndreas.Sandberg@ARM.com{ 1749428SAndreas.Sandberg@ARM.com using namespace TheISA; 1759428SAndreas.Sandberg@ARM.com 1769428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1779428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1789428SAndreas.Sandberg@ARM.com // compatibility. 17910905Sandreas.sandberg@arm.com arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1809428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1819428SAndreas.Sandberg@ARM.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 1829428SAndreas.Sandberg@ARM.com 1839428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1849428SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 1859428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1869428SAndreas.Sandberg@ARM.com tc.setIntRegFlat(i, intRegs[i]); 1879428SAndreas.Sandberg@ARM.com 1889920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1899920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 1909920Syasuko.eckert@amd.com UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 1919920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 1929920Syasuko.eckert@amd.com tc.setCCRegFlat(i, ccRegs[i]); 1939920Syasuko.eckert@amd.com#endif 1949920Syasuko.eckert@amd.com 1959428SAndreas.Sandberg@ARM.com PCState pcState; 19610905Sandreas.sandberg@arm.com pcState.unserialize(cp); 1979428SAndreas.Sandberg@ARM.com tc.pcState(pcState); 1989428SAndreas.Sandberg@ARM.com 1999428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 2009428SAndreas.Sandberg@ARM.com} 2019441SAndreas.Sandberg@ARM.com 2029441SAndreas.Sandberg@ARM.comvoid 2039441SAndreas.Sandberg@ARM.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 2049441SAndreas.Sandberg@ARM.com{ 2059441SAndreas.Sandberg@ARM.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 2069441SAndreas.Sandberg@ARM.com 2079441SAndreas.Sandberg@ARM.com ntc.setStatus(otc.status()); 2089441SAndreas.Sandberg@ARM.com ntc.copyArchRegs(&otc); 2099441SAndreas.Sandberg@ARM.com ntc.setContextId(otc.contextId()); 2109441SAndreas.Sandberg@ARM.com ntc.setThreadId(otc.threadId()); 2119441SAndreas.Sandberg@ARM.com 2129441SAndreas.Sandberg@ARM.com if (FullSystem) { 2139441SAndreas.Sandberg@ARM.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 2149441SAndreas.Sandberg@ARM.com 2159441SAndreas.Sandberg@ARM.com BaseCPU *ncpu(ntc.getCpuPtr()); 2169441SAndreas.Sandberg@ARM.com assert(ncpu); 2179441SAndreas.Sandberg@ARM.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 2189441SAndreas.Sandberg@ARM.com assert(oqe); 2199441SAndreas.Sandberg@ARM.com assert(oqe->tc == &otc); 2209441SAndreas.Sandberg@ARM.com 2219441SAndreas.Sandberg@ARM.com BaseCPU *ocpu(otc.getCpuPtr()); 2229441SAndreas.Sandberg@ARM.com assert(ocpu); 2239441SAndreas.Sandberg@ARM.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 2249441SAndreas.Sandberg@ARM.com assert(nqe); 2259441SAndreas.Sandberg@ARM.com assert(nqe->tc == &ntc); 2269441SAndreas.Sandberg@ARM.com 2279441SAndreas.Sandberg@ARM.com if (oqe->scheduled()) { 2289441SAndreas.Sandberg@ARM.com ncpu->schedule(nqe, oqe->when()); 2299441SAndreas.Sandberg@ARM.com ocpu->deschedule(oqe); 2309441SAndreas.Sandberg@ARM.com } 2319441SAndreas.Sandberg@ARM.com } 2329441SAndreas.Sandberg@ARM.com 2339441SAndreas.Sandberg@ARM.com otc.setStatus(ThreadContext::Halted); 2349441SAndreas.Sandberg@ARM.com} 235