memtest.cc revision 7823
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Erik Hallnor 292665SN/A * Steve Reinhardt 302SN/A */ 312SN/A 322SN/A// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 332SN/A 341298SN/A#include <iomanip> 351298SN/A#include <set> 361259SN/A#include <string> 372SN/A#include <vector> 382SN/A 39146SN/A#include "base/misc.hh" 40146SN/A#include "base/statistics.hh" 417632SBrad.Beckmann@amd.com#include "cpu/testers/memtest/memtest.hh" 423348SN/A#include "mem/mem_object.hh" 433348SN/A#include "mem/port.hh" 443348SN/A#include "mem/packet.hh" 453348SN/A#include "mem/request.hh" 4656SN/A#include "sim/sim_events.hh" 47695SN/A#include "sim/stats.hh" 482SN/A 492SN/Ausing namespace std; 502SN/A 511298SN/Aint TESTER_ALLOCATOR=0; 521298SN/A 533187SN/Abool 543349SN/AMemTest::CpuPort::recvTiming(PacketPtr pkt) 553187SN/A{ 564898SN/A if (pkt->isResponse()) { 574898SN/A memtest->completeRequest(pkt); 584898SN/A } else { 594898SN/A // must be snoop upcall 604898SN/A assert(pkt->isRequest()); 614898SN/A assert(pkt->getDest() == Packet::Broadcast); 624898SN/A } 633187SN/A return true; 643187SN/A} 653187SN/A 663187SN/ATick 673349SN/AMemTest::CpuPort::recvAtomic(PacketPtr pkt) 683187SN/A{ 694895SN/A // must be snoop upcall 704895SN/A assert(pkt->isRequest()); 714895SN/A assert(pkt->getDest() == Packet::Broadcast); 727823Ssteve.reinhardt@amd.com return curTick(); 733187SN/A} 743187SN/A 753187SN/Avoid 763349SN/AMemTest::CpuPort::recvFunctional(PacketPtr pkt) 773187SN/A{ 783204SN/A //Do nothing if we see one come through 797823Ssteve.reinhardt@amd.com// if (curTick() != 0)//Supress warning durring initialization 803340SN/A// warn("Functional Writes not implemented in MemTester\n"); 813262SN/A //Need to find any response values that intersect and update 823204SN/A return; 833187SN/A} 843187SN/A 853187SN/Avoid 863187SN/AMemTest::CpuPort::recvStatusChange(Status status) 873187SN/A{ 883647SN/A if (status == RangeChange) { 893647SN/A if (!snoopRangeSent) { 903647SN/A snoopRangeSent = true; 913647SN/A sendStatusChange(Port::RangeChange); 923647SN/A } 933187SN/A return; 943647SN/A } 953187SN/A 963187SN/A panic("MemTest doesn't expect recvStatusChange callback!"); 973187SN/A} 983187SN/A 993187SN/Avoid 1003187SN/AMemTest::CpuPort::recvRetry() 1013187SN/A{ 1023187SN/A memtest->doRetry(); 1033187SN/A} 1043187SN/A 1053262SN/Avoid 1063349SN/AMemTest::sendPkt(PacketPtr pkt) { 1073262SN/A if (atomic) { 1083262SN/A cachePort.sendAtomic(pkt); 1093262SN/A completeRequest(pkt); 1103262SN/A } 1113262SN/A else if (!cachePort.sendTiming(pkt)) { 1127544SN/A DPRINTF(MemTest, "accessRetry setting to true\n"); 1137544SN/A 1147544SN/A // 1157544SN/A // dma requests should never be retried 1167544SN/A // 1177544SN/A if (issueDmas) { 1187544SN/A panic("Nacked DMA requests are not supported\n"); 1197544SN/A } 1203262SN/A accessRetry = true; 1213262SN/A retryPkt = pkt; 1227544SN/A } else { 1237544SN/A if (issueDmas) { 1247544SN/A dmaOutstanding = true; 1257544SN/A } 1263262SN/A } 1273262SN/A 1283262SN/A} 1293262SN/A 1305034SN/AMemTest::MemTest(const Params *p) 1315034SN/A : MemObject(p), 1322SN/A tickEvent(this), 1333187SN/A cachePort("test", this), 1343187SN/A funcPort("functional", this), 1353187SN/A retryPkt(NULL), 1363187SN/A// mainMem(main_mem), 1373187SN/A// checkMem(check_mem), 1385034SN/A size(p->memory_size), 1395034SN/A percentReads(p->percent_reads), 1405034SN/A percentFunctional(p->percent_functional), 1415034SN/A percentUncacheable(p->percent_uncacheable), 1427544SN/A issueDmas(p->issue_dmas), 1435034SN/A progressInterval(p->progress_interval), 1445034SN/A nextProgressMessage(p->progress_interval), 1455034SN/A percentSourceUnaligned(p->percent_source_unaligned), 1465034SN/A percentDestUnaligned(p->percent_dest_unaligned), 1475034SN/A maxLoads(p->max_loads), 1485034SN/A atomic(p->atomic) 1492SN/A{ 1503647SN/A cachePort.snoopRangeSent = false; 1513647SN/A funcPort.snoopRangeSent = true; 1523647SN/A 1537544SN/A id = TESTER_ALLOCATOR++; 1547544SN/A 1553187SN/A // Needs to be masked off once we know the block size. 1565034SN/A traceBlockAddr = p->trace_addr; 1572SN/A baseAddr1 = 0x100000; 1582SN/A baseAddr2 = 0x400000; 1592SN/A uncacheAddr = 0x800000; 1602SN/A 1612SN/A // set up counters 1622SN/A noResponseCycles = 0; 1632SN/A numReads = 0; 1645606SN/A schedule(tickEvent, 0); 1651298SN/A 1663187SN/A accessRetry = false; 1677544SN/A dmaOutstanding = false; 1683187SN/A} 1693187SN/A 1703187SN/APort * 1713187SN/AMemTest::getPort(const std::string &if_name, int idx) 1723187SN/A{ 1733187SN/A if (if_name == "functional") 1743187SN/A return &funcPort; 1753187SN/A else if (if_name == "test") 1763187SN/A return &cachePort; 1773187SN/A else 1783187SN/A panic("No Such Port\n"); 1793187SN/A} 1803187SN/A 1813187SN/Avoid 1823187SN/AMemTest::init() 1833187SN/A{ 1843187SN/A // By the time init() is called, the ports should be hooked up. 1853187SN/A blockSize = cachePort.peerBlockSize(); 1863187SN/A blockAddrMask = blockSize - 1; 1873187SN/A traceBlockAddr = blockAddr(traceBlockAddr); 1883187SN/A 1894579SN/A // initial memory contents for both physical memory and functional 1904579SN/A // memory should be 0; no need to initialize them. 1912SN/A} 1922SN/A 1932SN/A 1942SN/Avoid 1953349SN/AMemTest::completeRequest(PacketPtr pkt) 1962SN/A{ 1974628SN/A Request *req = pkt->req; 1984628SN/A 1997544SN/A if (issueDmas) { 2007544SN/A dmaOutstanding = false; 2017544SN/A } 2027544SN/A 2034628SN/A DPRINTF(MemTest, "completing %s at address %x (blk %x)\n", 2044628SN/A pkt->isWrite() ? "write" : "read", 2054628SN/A req->getPaddr(), blockAddr(req->getPaddr())); 2064628SN/A 2073187SN/A MemTestSenderState *state = 2083187SN/A dynamic_cast<MemTestSenderState *>(pkt->senderState); 2093187SN/A 2103187SN/A uint8_t *data = state->data; 2113187SN/A uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 2123187SN/A 2131298SN/A //Remove the address from the list of outstanding 2144628SN/A std::set<unsigned>::iterator removeAddr = 2154628SN/A outstandingAddrs.find(req->getPaddr()); 2161298SN/A assert(removeAddr != outstandingAddrs.end()); 2171298SN/A outstandingAddrs.erase(removeAddr); 2181298SN/A 2195319SN/A if (pkt->isRead()) { 2203187SN/A if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 2214626SN/A panic("%s: read of %x (blk %x) @ cycle %d " 2224626SN/A "returns %x, expected %x\n", name(), 2237823Ssteve.reinhardt@amd.com req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 2244626SN/A *pkt_data, *data); 2252SN/A } 2262SN/A 2272SN/A numReads++; 228695SN/A numReadsStat++; 2292SN/A 2306227SN/A if (numReads == (uint64_t)nextProgressMessage) { 231695SN/A ccprintf(cerr, "%s: completed %d read accesses @%d\n", 2327823Ssteve.reinhardt@amd.com name(), numReads, curTick()); 2332SN/A nextProgressMessage += progressInterval; 2342SN/A } 2352SN/A 2364893SN/A if (maxLoads != 0 && numReads >= maxLoads) 2374628SN/A exitSimLoop("maximum number of loads reached"); 2385319SN/A } else { 2395319SN/A assert(pkt->isWrite()); 240695SN/A numWritesStat++; 2412SN/A } 2422SN/A 2432SN/A noResponseCycles = 0; 2443187SN/A delete state; 2452SN/A delete [] data; 2463187SN/A delete pkt->req; 2473187SN/A delete pkt; 2482SN/A} 2492SN/A 2502SN/Avoid 2512SN/AMemTest::regStats() 2522SN/A{ 253729SN/A using namespace Stats; 2542SN/A 255695SN/A numReadsStat 2562SN/A .name(name() + ".num_reads") 2572SN/A .desc("number of read accesses completed") 2582SN/A ; 2592SN/A 260695SN/A numWritesStat 2612SN/A .name(name() + ".num_writes") 2622SN/A .desc("number of write accesses completed") 2632SN/A ; 2642SN/A 265695SN/A numCopiesStat 2662SN/A .name(name() + ".num_copies") 2672SN/A .desc("number of copy accesses completed") 2682SN/A ; 2692SN/A} 2702SN/A 2712SN/Avoid 2722SN/AMemTest::tick() 2732SN/A{ 2742SN/A if (!tickEvent.scheduled()) 2757823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + ticks(1)); 2762SN/A 2771298SN/A if (++noResponseCycles >= 500000) { 2787544SN/A if (issueDmas) { 2797544SN/A cerr << "DMA tester "; 2807544SN/A } 2817823Ssteve.reinhardt@amd.com cerr << name() << ": deadlocked at cycle " << curTick() << endl; 2822SN/A fatal(""); 2832SN/A } 2842SN/A 2857544SN/A if (accessRetry || (issueDmas && dmaOutstanding)) { 2867544SN/A DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 2872SN/A return; 2882SN/A } 2892SN/A 2902SN/A //make new request 2911899SN/A unsigned cmd = random() % 100; 2921899SN/A unsigned offset = random() % size; 2932SN/A unsigned base = random() % 2; 2942SN/A uint64_t data = random(); 2952SN/A unsigned access_size = random() % 4; 2965736SN/A bool uncacheable = (random() % 100) < percentUncacheable; 2972SN/A 2987544SN/A unsigned dma_access_size = random() % 4; 2997544SN/A 3001298SN/A //If we aren't doing copies, use id as offset, and do a false sharing 3011298SN/A //mem tester 3023187SN/A //We can eliminate the lower bits of the offset, and then use the id 3033187SN/A //to offset within the blks 3044628SN/A offset = blockAddr(offset); 3053187SN/A offset += id; 3063187SN/A access_size = 0; 3077544SN/A dma_access_size = 0; 3081298SN/A 3093187SN/A Request *req = new Request(); 3105736SN/A Request::Flags flags; 3113187SN/A Addr paddr; 3122SN/A 3135736SN/A if (uncacheable) { 3145736SN/A flags.set(Request::UNCACHEABLE); 3153187SN/A paddr = uncacheAddr + offset; 3167544SN/A } else { 3173187SN/A paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 3182SN/A } 3197657Ssteve.reinhardt@amd.com bool do_functional = (random() % 100 < percentFunctional) && !uncacheable; 3202SN/A 3217544SN/A if (issueDmas) { 3227544SN/A paddr &= ~((1 << dma_access_size) - 1); 3237544SN/A req->setPhys(paddr, 1 << dma_access_size, flags); 3247544SN/A req->setThreadContext(id,0); 3257544SN/A } else { 3267544SN/A paddr &= ~((1 << access_size) - 1); 3277544SN/A req->setPhys(paddr, 1 << access_size, flags); 3287544SN/A req->setThreadContext(id,0); 3297544SN/A } 3307544SN/A assert(req->getSize() == 1); 3313187SN/A 3323187SN/A uint8_t *result = new uint8_t[8]; 3332SN/A 3342SN/A if (cmd < percentReads) { 3352SN/A // read 3361298SN/A 3374628SN/A // For now we only allow one outstanding request per address 3384628SN/A // per tester This means we assume CPU does write forwarding 3394628SN/A // to reads that alias something in the cpu store buffer. 3403282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3414203SN/A delete [] result; 3423282SN/A delete req; 3433282SN/A return; 3443282SN/A } 3454628SN/A 3464628SN/A outstandingAddrs.insert(paddr); 3471298SN/A 3483187SN/A // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 3493187SN/A funcPort.readBlob(req->getPaddr(), result, req->getSize()); 3503187SN/A 3514628SN/A DPRINTF(MemTest, 3527657Ssteve.reinhardt@amd.com "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 3537657Ssteve.reinhardt@amd.com id, do_functional ? "functional " : "", req->getPaddr(), 3547657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), *result); 3553187SN/A 3564022SN/A PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 3574660SN/A pkt->setSrc(0); 3583187SN/A pkt->dataDynamicArray(new uint8_t[req->getSize()]); 3593187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3603187SN/A pkt->senderState = state; 3613187SN/A 3627657Ssteve.reinhardt@amd.com if (do_functional) { 3633187SN/A cachePort.sendFunctional(pkt); 3643204SN/A completeRequest(pkt); 365145SN/A } else { 3663262SN/A sendPkt(pkt); 367145SN/A } 3683187SN/A } else { 3692SN/A // write 3701298SN/A 3714628SN/A // For now we only allow one outstanding request per addreess 3724628SN/A // per tester. This means we assume CPU does write forwarding 3734628SN/A // to reads that alias something in the cpu store buffer. 3743282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3753283SN/A delete [] result; 3763282SN/A delete req; 3773282SN/A return; 3783282SN/A } 3793282SN/A 3804628SN/A outstandingAddrs.insert(paddr); 3811298SN/A 3827657Ssteve.reinhardt@amd.com DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 3837657Ssteve.reinhardt@amd.com do_functional ? "functional " : "", req->getPaddr(), 3847657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), data & 0xff); 3854628SN/A 3864022SN/A PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 3874660SN/A pkt->setSrc(0); 3883187SN/A uint8_t *pkt_data = new uint8_t[req->getSize()]; 3893187SN/A pkt->dataDynamicArray(pkt_data); 3903187SN/A memcpy(pkt_data, &data, req->getSize()); 3913187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3923187SN/A pkt->senderState = state; 3933187SN/A 3943187SN/A funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 3953187SN/A 3967657Ssteve.reinhardt@amd.com if (do_functional) { 3973187SN/A cachePort.sendFunctional(pkt); 3983262SN/A completeRequest(pkt); 399145SN/A } else { 4003262SN/A sendPkt(pkt); 401145SN/A } 4023187SN/A } 4032SN/A} 4042SN/A 4052SN/Avoid 4063187SN/AMemTest::doRetry() 4072SN/A{ 4083187SN/A if (cachePort.sendTiming(retryPkt)) { 4097544SN/A DPRINTF(MemTest, "accessRetry setting to false\n"); 4103187SN/A accessRetry = false; 4113187SN/A retryPkt = NULL; 4123187SN/A } 4132SN/A} 4142SN/A 4155314SN/A 4165314SN/Avoid 4175314SN/AMemTest::printAddr(Addr a) 4185314SN/A{ 4195314SN/A cachePort.printAddr(a); 4205314SN/A} 4215315SN/A 4225315SN/A 4235315SN/AMemTest * 4245315SN/AMemTestParams::create() 4255315SN/A{ 4265315SN/A return new MemTest(this); 4275315SN/A} 428