memtest.cc revision 7823
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/statistics.hh" 41#include "cpu/testers/memtest/memtest.hh" 42#include "mem/mem_object.hh" 43#include "mem/port.hh" 44#include "mem/packet.hh" 45#include "mem/request.hh" 46#include "sim/sim_events.hh" 47#include "sim/stats.hh" 48 49using namespace std; 50 51int TESTER_ALLOCATOR=0; 52 53bool 54MemTest::CpuPort::recvTiming(PacketPtr pkt) 55{ 56 if (pkt->isResponse()) { 57 memtest->completeRequest(pkt); 58 } else { 59 // must be snoop upcall 60 assert(pkt->isRequest()); 61 assert(pkt->getDest() == Packet::Broadcast); 62 } 63 return true; 64} 65 66Tick 67MemTest::CpuPort::recvAtomic(PacketPtr pkt) 68{ 69 // must be snoop upcall 70 assert(pkt->isRequest()); 71 assert(pkt->getDest() == Packet::Broadcast); 72 return curTick(); 73} 74 75void 76MemTest::CpuPort::recvFunctional(PacketPtr pkt) 77{ 78 //Do nothing if we see one come through 79// if (curTick() != 0)//Supress warning durring initialization 80// warn("Functional Writes not implemented in MemTester\n"); 81 //Need to find any response values that intersect and update 82 return; 83} 84 85void 86MemTest::CpuPort::recvStatusChange(Status status) 87{ 88 if (status == RangeChange) { 89 if (!snoopRangeSent) { 90 snoopRangeSent = true; 91 sendStatusChange(Port::RangeChange); 92 } 93 return; 94 } 95 96 panic("MemTest doesn't expect recvStatusChange callback!"); 97} 98 99void 100MemTest::CpuPort::recvRetry() 101{ 102 memtest->doRetry(); 103} 104 105void 106MemTest::sendPkt(PacketPtr pkt) { 107 if (atomic) { 108 cachePort.sendAtomic(pkt); 109 completeRequest(pkt); 110 } 111 else if (!cachePort.sendTiming(pkt)) { 112 DPRINTF(MemTest, "accessRetry setting to true\n"); 113 114 // 115 // dma requests should never be retried 116 // 117 if (issueDmas) { 118 panic("Nacked DMA requests are not supported\n"); 119 } 120 accessRetry = true; 121 retryPkt = pkt; 122 } else { 123 if (issueDmas) { 124 dmaOutstanding = true; 125 } 126 } 127 128} 129 130MemTest::MemTest(const Params *p) 131 : MemObject(p), 132 tickEvent(this), 133 cachePort("test", this), 134 funcPort("functional", this), 135 retryPkt(NULL), 136// mainMem(main_mem), 137// checkMem(check_mem), 138 size(p->memory_size), 139 percentReads(p->percent_reads), 140 percentFunctional(p->percent_functional), 141 percentUncacheable(p->percent_uncacheable), 142 issueDmas(p->issue_dmas), 143 progressInterval(p->progress_interval), 144 nextProgressMessage(p->progress_interval), 145 percentSourceUnaligned(p->percent_source_unaligned), 146 percentDestUnaligned(p->percent_dest_unaligned), 147 maxLoads(p->max_loads), 148 atomic(p->atomic) 149{ 150 cachePort.snoopRangeSent = false; 151 funcPort.snoopRangeSent = true; 152 153 id = TESTER_ALLOCATOR++; 154 155 // Needs to be masked off once we know the block size. 156 traceBlockAddr = p->trace_addr; 157 baseAddr1 = 0x100000; 158 baseAddr2 = 0x400000; 159 uncacheAddr = 0x800000; 160 161 // set up counters 162 noResponseCycles = 0; 163 numReads = 0; 164 schedule(tickEvent, 0); 165 166 accessRetry = false; 167 dmaOutstanding = false; 168} 169 170Port * 171MemTest::getPort(const std::string &if_name, int idx) 172{ 173 if (if_name == "functional") 174 return &funcPort; 175 else if (if_name == "test") 176 return &cachePort; 177 else 178 panic("No Such Port\n"); 179} 180 181void 182MemTest::init() 183{ 184 // By the time init() is called, the ports should be hooked up. 185 blockSize = cachePort.peerBlockSize(); 186 blockAddrMask = blockSize - 1; 187 traceBlockAddr = blockAddr(traceBlockAddr); 188 189 // initial memory contents for both physical memory and functional 190 // memory should be 0; no need to initialize them. 191} 192 193 194void 195MemTest::completeRequest(PacketPtr pkt) 196{ 197 Request *req = pkt->req; 198 199 if (issueDmas) { 200 dmaOutstanding = false; 201 } 202 203 DPRINTF(MemTest, "completing %s at address %x (blk %x)\n", 204 pkt->isWrite() ? "write" : "read", 205 req->getPaddr(), blockAddr(req->getPaddr())); 206 207 MemTestSenderState *state = 208 dynamic_cast<MemTestSenderState *>(pkt->senderState); 209 210 uint8_t *data = state->data; 211 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 212 213 //Remove the address from the list of outstanding 214 std::set<unsigned>::iterator removeAddr = 215 outstandingAddrs.find(req->getPaddr()); 216 assert(removeAddr != outstandingAddrs.end()); 217 outstandingAddrs.erase(removeAddr); 218 219 if (pkt->isRead()) { 220 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 221 panic("%s: read of %x (blk %x) @ cycle %d " 222 "returns %x, expected %x\n", name(), 223 req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 224 *pkt_data, *data); 225 } 226 227 numReads++; 228 numReadsStat++; 229 230 if (numReads == (uint64_t)nextProgressMessage) { 231 ccprintf(cerr, "%s: completed %d read accesses @%d\n", 232 name(), numReads, curTick()); 233 nextProgressMessage += progressInterval; 234 } 235 236 if (maxLoads != 0 && numReads >= maxLoads) 237 exitSimLoop("maximum number of loads reached"); 238 } else { 239 assert(pkt->isWrite()); 240 numWritesStat++; 241 } 242 243 noResponseCycles = 0; 244 delete state; 245 delete [] data; 246 delete pkt->req; 247 delete pkt; 248} 249 250void 251MemTest::regStats() 252{ 253 using namespace Stats; 254 255 numReadsStat 256 .name(name() + ".num_reads") 257 .desc("number of read accesses completed") 258 ; 259 260 numWritesStat 261 .name(name() + ".num_writes") 262 .desc("number of write accesses completed") 263 ; 264 265 numCopiesStat 266 .name(name() + ".num_copies") 267 .desc("number of copy accesses completed") 268 ; 269} 270 271void 272MemTest::tick() 273{ 274 if (!tickEvent.scheduled()) 275 schedule(tickEvent, curTick() + ticks(1)); 276 277 if (++noResponseCycles >= 500000) { 278 if (issueDmas) { 279 cerr << "DMA tester "; 280 } 281 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 282 fatal(""); 283 } 284 285 if (accessRetry || (issueDmas && dmaOutstanding)) { 286 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 287 return; 288 } 289 290 //make new request 291 unsigned cmd = random() % 100; 292 unsigned offset = random() % size; 293 unsigned base = random() % 2; 294 uint64_t data = random(); 295 unsigned access_size = random() % 4; 296 bool uncacheable = (random() % 100) < percentUncacheable; 297 298 unsigned dma_access_size = random() % 4; 299 300 //If we aren't doing copies, use id as offset, and do a false sharing 301 //mem tester 302 //We can eliminate the lower bits of the offset, and then use the id 303 //to offset within the blks 304 offset = blockAddr(offset); 305 offset += id; 306 access_size = 0; 307 dma_access_size = 0; 308 309 Request *req = new Request(); 310 Request::Flags flags; 311 Addr paddr; 312 313 if (uncacheable) { 314 flags.set(Request::UNCACHEABLE); 315 paddr = uncacheAddr + offset; 316 } else { 317 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 318 } 319 bool do_functional = (random() % 100 < percentFunctional) && !uncacheable; 320 321 if (issueDmas) { 322 paddr &= ~((1 << dma_access_size) - 1); 323 req->setPhys(paddr, 1 << dma_access_size, flags); 324 req->setThreadContext(id,0); 325 } else { 326 paddr &= ~((1 << access_size) - 1); 327 req->setPhys(paddr, 1 << access_size, flags); 328 req->setThreadContext(id,0); 329 } 330 assert(req->getSize() == 1); 331 332 uint8_t *result = new uint8_t[8]; 333 334 if (cmd < percentReads) { 335 // read 336 337 // For now we only allow one outstanding request per address 338 // per tester This means we assume CPU does write forwarding 339 // to reads that alias something in the cpu store buffer. 340 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 341 delete [] result; 342 delete req; 343 return; 344 } 345 346 outstandingAddrs.insert(paddr); 347 348 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 349 funcPort.readBlob(req->getPaddr(), result, req->getSize()); 350 351 DPRINTF(MemTest, 352 "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 353 id, do_functional ? "functional " : "", req->getPaddr(), 354 blockAddr(req->getPaddr()), *result); 355 356 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 357 pkt->setSrc(0); 358 pkt->dataDynamicArray(new uint8_t[req->getSize()]); 359 MemTestSenderState *state = new MemTestSenderState(result); 360 pkt->senderState = state; 361 362 if (do_functional) { 363 cachePort.sendFunctional(pkt); 364 completeRequest(pkt); 365 } else { 366 sendPkt(pkt); 367 } 368 } else { 369 // write 370 371 // For now we only allow one outstanding request per addreess 372 // per tester. This means we assume CPU does write forwarding 373 // to reads that alias something in the cpu store buffer. 374 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 375 delete [] result; 376 delete req; 377 return; 378 } 379 380 outstandingAddrs.insert(paddr); 381 382 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 383 do_functional ? "functional " : "", req->getPaddr(), 384 blockAddr(req->getPaddr()), data & 0xff); 385 386 PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 387 pkt->setSrc(0); 388 uint8_t *pkt_data = new uint8_t[req->getSize()]; 389 pkt->dataDynamicArray(pkt_data); 390 memcpy(pkt_data, &data, req->getSize()); 391 MemTestSenderState *state = new MemTestSenderState(result); 392 pkt->senderState = state; 393 394 funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 395 396 if (do_functional) { 397 cachePort.sendFunctional(pkt); 398 completeRequest(pkt); 399 } else { 400 sendPkt(pkt); 401 } 402 } 403} 404 405void 406MemTest::doRetry() 407{ 408 if (cachePort.sendTiming(retryPkt)) { 409 DPRINTF(MemTest, "accessRetry setting to false\n"); 410 accessRetry = false; 411 retryPkt = NULL; 412 } 413} 414 415 416void 417MemTest::printAddr(Addr a) 418{ 419 cachePort.printAddr(a); 420} 421 422 423MemTest * 424MemTestParams::create() 425{ 426 return new MemTest(this); 427} 428