simple_thread.hh revision 6323
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 373776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 422680SN/A#include "cpu/thread_context.hh" 432683Sktlim@umich.edu#include "cpu/thread_state.hh" 442395SN/A#include "mem/request.hh" 452190SN/A#include "sim/byteswap.hh" 462188SN/A#include "sim/eventq.hh" 47217SN/A#include "sim/serialize.hh" 482SN/A 492SN/Aclass BaseCPU; 502SN/A 511858SN/A#if FULL_SYSTEM 522SN/A 531070SN/A#include "sim/system.hh" 541070SN/A 551917SN/Aclass FunctionProfile; 561917SN/Aclass ProfileNode; 572521SN/Aclass FunctionalPort; 582521SN/Aclass PhysicalPort; 592521SN/A 603548Sgblack@eecs.umich.edunamespace TheISA { 613548Sgblack@eecs.umich.edu namespace Kernel { 623548Sgblack@eecs.umich.edu class Statistics; 633548Sgblack@eecs.umich.edu }; 642330SN/A}; 652330SN/A 662SN/A#else // !FULL_SYSTEM 672SN/A 68360SN/A#include "sim/process.hh" 692462SN/A#include "mem/page_table.hh" 702420SN/Aclass TranslatingPort; 712SN/A 722SN/A#endif // FULL_SYSTEM 732SN/A 742683Sktlim@umich.edu/** 752683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 762683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 772683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 782683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 792683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 802683Sktlim@umich.edu * the objects needed for simple functional execution, including a 812683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 822683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 832683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 842683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 852683Sktlim@umich.edu * all the necessary state for full architecture-level functional 862683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 872683Sktlim@umich.edu * examples. 882683Sktlim@umich.edu */ 892SN/A 902683Sktlim@umich.educlass SimpleThread : public ThreadState 912SN/A{ 922107SN/A protected: 932107SN/A typedef TheISA::RegFile RegFile; 942107SN/A typedef TheISA::MachInst MachInst; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1025543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1036315Sgblack@eecs.umich.edu union { 1046315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1056315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1066315Sgblack@eecs.umich.edu } floatRegs; 1076316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1086313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1092SN/A 1102190SN/A public: 1112683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1122SN/A BaseCPU *cpu; 1132SN/A 1142683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1152188SN/A 1162378SN/A System *system; 1172400SN/A 1186022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1196022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1202SN/A 1212683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1221858SN/A#if FULL_SYSTEM 1232683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1246022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1252683Sktlim@umich.edu bool use_kernel_stats = true); 1262SN/A#else 1274997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1286022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 1292SN/A#endif 1302862Sktlim@umich.edu 1312864Sktlim@umich.edu SimpleThread(); 1322862Sktlim@umich.edu 1332683Sktlim@umich.edu virtual ~SimpleThread(); 1342SN/A 1352680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 136180SN/A 1372SN/A void regStats(const std::string &name); 1382SN/A 1392864Sktlim@umich.edu void copyTC(ThreadContext *context); 1402864Sktlim@umich.edu 1412862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1422862Sktlim@umich.edu 143217SN/A void serialize(std::ostream &os); 144237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 145217SN/A 1462683Sktlim@umich.edu /*************************************************************** 1472683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1485891Sgblack@eecs.umich.edu * state. 1492683Sktlim@umich.edu **************************************************************/ 1502190SN/A 1512683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1522683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1532683Sktlim@umich.edu * CPU. 1542683Sktlim@umich.edu */ 1552680SN/A ThreadContext *getTC() { return tc; } 1562190SN/A 1575358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1585358Sgblack@eecs.umich.edu { 1595358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1605358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1615358Sgblack@eecs.umich.edu } 1625358Sgblack@eecs.umich.edu 1635358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1645358Sgblack@eecs.umich.edu { 1655358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1665358Sgblack@eecs.umich.edu } 1675358Sgblack@eecs.umich.edu 1685358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1695358Sgblack@eecs.umich.edu { 1705358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1715358Sgblack@eecs.umich.edu } 1725358Sgblack@eecs.umich.edu 1734997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1746313Sgblack@eecs.umich.edu int getInstAsid() { return isa.instAsid(); } 1756313Sgblack@eecs.umich.edu int getDataAsid() { return isa.dataAsid(); } 1764997Sgblack@eecs.umich.edu 1772683Sktlim@umich.edu void dumpFuncProfile(); 1782521SN/A 1795702Ssaidi@eecs.umich.edu Fault hwrei(); 1805702Ssaidi@eecs.umich.edu 1815702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1825702Ssaidi@eecs.umich.edu 1832683Sktlim@umich.edu#endif 1842SN/A 1852683Sktlim@umich.edu /******************************************* 1862683Sktlim@umich.edu * ThreadContext interface functions. 1872683Sktlim@umich.edu ******************************************/ 1882683Sktlim@umich.edu 1892683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1902683Sktlim@umich.edu 1916022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1922683Sktlim@umich.edu 1936022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1942683Sktlim@umich.edu 1954997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1964997Sgblack@eecs.umich.edu 1975803Snate@binkert.org#if FULL_SYSTEM 1982683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1992683Sktlim@umich.edu 2005499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2015499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2025499Ssaidi@eecs.umich.edu * mean stale data. 2035499Ssaidi@eecs.umich.edu */ 2045499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2052SN/A#endif 2062SN/A 2072683Sktlim@umich.edu Status status() const { return _status; } 2082683Sktlim@umich.edu 2092683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2122683Sktlim@umich.edu /// cycles to wait before beginning execution. 2132683Sktlim@umich.edu void activate(int delay = 1); 2142683Sktlim@umich.edu 2152683Sktlim@umich.edu /// Set the status to Suspended. 2162683Sktlim@umich.edu void suspend(); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Halted. 2192683Sktlim@umich.edu void halt(); 2202683Sktlim@umich.edu 2212SN/A virtual bool misspeculating(); 2222SN/A 2232532SN/A Fault instRead(RequestPtr &req) 224716SN/A { 2252378SN/A panic("instRead not implemented"); 2262378SN/A // return funcPhysMem->read(req, inst); 2272423SN/A return NoFault; 228716SN/A } 229716SN/A 2302683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2312190SN/A 2326315Sgblack@eecs.umich.edu void clearArchRegs() 2336315Sgblack@eecs.umich.edu { 2346315Sgblack@eecs.umich.edu regs.clear(); 2356316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2366315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2376315Sgblack@eecs.umich.edu } 2382190SN/A 2392SN/A // 2402SN/A // New accessors for new decoder. 2412SN/A // 2422SN/A uint64_t readIntReg(int reg_idx) 2432SN/A { 2446313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2456323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2466316Sgblack@eecs.umich.edu return intRegs[flatIndex]; 2472SN/A } 2482SN/A 2492455SN/A FloatReg readFloatReg(int reg_idx) 2502SN/A { 2516313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2526323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2536315Sgblack@eecs.umich.edu return floatRegs.f[flatIndex]; 2542SN/A } 2552SN/A 2562455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2572455SN/A { 2586313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2596323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2606315Sgblack@eecs.umich.edu return floatRegs.i[flatIndex]; 2612SN/A } 2622SN/A 2632SN/A void setIntReg(int reg_idx, uint64_t val) 2642SN/A { 2656313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2666323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2676316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2682SN/A } 2692SN/A 2702455SN/A void setFloatReg(int reg_idx, FloatReg val) 2712SN/A { 2726313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2736323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2746315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2752SN/A } 2762SN/A 2772455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2782455SN/A { 2796313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2806323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2816315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 2822SN/A } 2832SN/A 2842SN/A uint64_t readPC() 2852SN/A { 2862525SN/A return regs.readPC(); 2872SN/A } 2882SN/A 2892190SN/A void setPC(uint64_t val) 2902190SN/A { 2912525SN/A regs.setPC(val); 2922190SN/A } 2932190SN/A 2943276Sgblack@eecs.umich.edu uint64_t readMicroPC() 2953276Sgblack@eecs.umich.edu { 2963276Sgblack@eecs.umich.edu return microPC; 2973276Sgblack@eecs.umich.edu } 2983276Sgblack@eecs.umich.edu 2993276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3003276Sgblack@eecs.umich.edu { 3013276Sgblack@eecs.umich.edu microPC = val; 3023276Sgblack@eecs.umich.edu } 3033276Sgblack@eecs.umich.edu 3042190SN/A uint64_t readNextPC() 3052190SN/A { 3062525SN/A return regs.readNextPC(); 3072190SN/A } 3082190SN/A 3092SN/A void setNextPC(uint64_t val) 3102SN/A { 3112525SN/A regs.setNextPC(val); 3122SN/A } 3132SN/A 3143276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3153276Sgblack@eecs.umich.edu { 3163276Sgblack@eecs.umich.edu return nextMicroPC; 3173276Sgblack@eecs.umich.edu } 3183276Sgblack@eecs.umich.edu 3193276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3203276Sgblack@eecs.umich.edu { 3213276Sgblack@eecs.umich.edu nextMicroPC = val; 3223276Sgblack@eecs.umich.edu } 3233276Sgblack@eecs.umich.edu 3242252SN/A uint64_t readNextNPC() 3252252SN/A { 3262525SN/A return regs.readNextNPC(); 3272252SN/A } 3282252SN/A 3292251SN/A void setNextNPC(uint64_t val) 3302251SN/A { 3312525SN/A regs.setNextNPC(val); 3322251SN/A } 3332251SN/A 3346221Snate@binkert.org MiscReg 3356221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3364172Ssaidi@eecs.umich.edu { 3376313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3384172Ssaidi@eecs.umich.edu } 3394172Ssaidi@eecs.umich.edu 3406221Snate@binkert.org MiscReg 3416221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3422SN/A { 3436313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3442SN/A } 3452SN/A 3466221Snate@binkert.org void 3476221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3482SN/A { 3496313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3502SN/A } 3512SN/A 3526221Snate@binkert.org void 3536221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3542SN/A { 3556313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3566313Sgblack@eecs.umich.edu } 3576313Sgblack@eecs.umich.edu 3586313Sgblack@eecs.umich.edu int 3596313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3606313Sgblack@eecs.umich.edu { 3616313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3626313Sgblack@eecs.umich.edu } 3636313Sgblack@eecs.umich.edu 3646313Sgblack@eecs.umich.edu int 3656313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3666313Sgblack@eecs.umich.edu { 3676313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3682SN/A } 3692SN/A 3702190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3712190SN/A 3722190SN/A void setStCondFailures(unsigned sc_failures) 3732190SN/A { storeCondFailures = sc_failures; } 3742190SN/A 3751858SN/A#if !FULL_SYSTEM 3762561SN/A void syscall(int64_t callnum) 3772SN/A { 3782680SN/A process->syscall(callnum, tc); 3792SN/A } 3802SN/A#endif 3812SN/A}; 3822SN/A 3832SN/A 3842SN/A// for non-speculative execution context, spec_mode is always false 3852SN/Ainline bool 3862683Sktlim@umich.eduSimpleThread::misspeculating() 3872SN/A{ 3882SN/A return false; 3892SN/A} 3902SN/A 3912190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 392