timing.hh revision 8706:b1838faf3bcc 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40  public:
41
42    TimingSimpleCPU(TimingSimpleCPUParams * params);
43    virtual ~TimingSimpleCPU();
44
45    virtual void init();
46
47  public:
48    Event *drainEvent;
49
50  private:
51
52    /*
53     * If an access needs to be broken into fragments, currently at most two,
54     * the the following two classes are used as the sender state of the
55     * packets so the CPU can keep track of everything. In the main packet
56     * sender state, there's an array with a spot for each fragment. If a
57     * fragment has already been accepted by the CPU, aka isn't waiting for
58     * a retry, it's pointer is NULL. After each fragment has successfully
59     * been processed, the "outstanding" counter is decremented. Once the
60     * count is zero, the entire larger access is complete.
61     */
62    class SplitMainSenderState : public Packet::SenderState
63    {
64      public:
65        int outstanding;
66        PacketPtr fragments[2];
67
68        int
69        getPendingFragment()
70        {
71            if (fragments[0]) {
72                return 0;
73            } else if (fragments[1]) {
74                return 1;
75            } else {
76                return -1;
77            }
78        }
79    };
80
81    class SplitFragmentSenderState : public Packet::SenderState
82    {
83      public:
84        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85            bigPkt(_bigPkt), index(_index)
86        {}
87        PacketPtr bigPkt;
88        int index;
89
90        void
91        clearFromParent()
92        {
93            SplitMainSenderState * main_send_state =
94                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95            main_send_state->fragments[index] = NULL;
96        }
97    };
98
99    class FetchTranslation : public BaseTLB::Translation
100    {
101      protected:
102        TimingSimpleCPU *cpu;
103
104      public:
105        FetchTranslation(TimingSimpleCPU *_cpu)
106            : cpu(_cpu)
107        {}
108
109        void
110        markDelayed()
111        {
112            assert(cpu->_status == Running);
113            cpu->_status = ITBWaitResponse;
114        }
115
116        void
117        finish(Fault fault, RequestPtr req, ThreadContext *tc,
118               BaseTLB::Mode mode)
119        {
120            cpu->sendFetch(fault, req, tc);
121        }
122    };
123    FetchTranslation fetchTranslation;
124
125    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127                       uint8_t *data, bool read);
128
129    void translationFault(Fault fault);
130
131    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133            RequestPtr req1, RequestPtr req2, RequestPtr req,
134            uint8_t *data, bool read);
135
136    bool handleReadPacket(PacketPtr pkt);
137    // This function always implicitly uses dcache_pkt.
138    bool handleWritePacket();
139
140    class CpuPort : public Port
141    {
142      protected:
143        TimingSimpleCPU *cpu;
144        Tick lat;
145
146      public:
147
148        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
149            : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
150        { }
151
152        bool snoopRangeSent;
153
154      protected:
155
156        virtual Tick recvAtomic(PacketPtr pkt);
157
158        virtual void recvFunctional(PacketPtr pkt);
159
160        virtual void recvStatusChange(Status status);
161
162        virtual void getDeviceAddressRanges(AddrRangeList &resp,
163                                            bool &snoop)
164        { resp.clear(); snoop = false; }
165
166        struct TickEvent : public Event
167        {
168            PacketPtr pkt;
169            TimingSimpleCPU *cpu;
170            CpuPort *port;
171
172            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
173            const char *description() const { return "Timing CPU tick"; }
174            void schedule(PacketPtr _pkt, Tick t);
175        };
176
177        EventWrapper<Port, &Port::sendRetry> retryEvent;
178    };
179
180    class IcachePort : public CpuPort
181    {
182      public:
183
184        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
185            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
186        { }
187
188      protected:
189
190        virtual bool recvTiming(PacketPtr pkt);
191
192        virtual void recvRetry();
193
194        struct ITickEvent : public TickEvent
195        {
196
197            ITickEvent(TimingSimpleCPU *_cpu)
198                : TickEvent(_cpu) {}
199            void process();
200            const char *description() const { return "Timing CPU icache tick"; }
201        };
202
203        ITickEvent tickEvent;
204
205    };
206
207    class DcachePort : public CpuPort
208    {
209      public:
210
211        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
212            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
213        { }
214
215      protected:
216
217        virtual bool recvTiming(PacketPtr pkt);
218
219        virtual void recvRetry();
220
221        struct DTickEvent : public TickEvent
222        {
223            DTickEvent(TimingSimpleCPU *_cpu)
224                : TickEvent(_cpu) {}
225            void process();
226            const char *description() const { return "Timing CPU dcache tick"; }
227        };
228
229        DTickEvent tickEvent;
230
231    };
232
233    IcachePort icachePort;
234    DcachePort dcachePort;
235
236    PacketPtr ifetch_pkt;
237    PacketPtr dcache_pkt;
238
239    Tick previousTick;
240
241  public:
242
243    virtual Port *getPort(const std::string &if_name, int idx = -1);
244
245    virtual void serialize(std::ostream &os);
246    virtual void unserialize(Checkpoint *cp, const std::string &section);
247
248    virtual unsigned int drain(Event *drain_event);
249    virtual void resume();
250
251    void switchOut();
252    void takeOverFrom(BaseCPU *oldCPU);
253
254    virtual void activateContext(int thread_num, int delay);
255    virtual void suspendContext(int thread_num);
256
257    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
258
259    Fault writeMem(uint8_t *data, unsigned size,
260                   Addr addr, unsigned flags, uint64_t *res);
261
262    void fetch();
263    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
264    void completeIfetch(PacketPtr );
265    void completeDataAccess(PacketPtr pkt);
266    void advanceInst(Fault fault);
267
268    /**
269     * Print state of address in memory system via PrintReq (for
270     * debugging).
271     */
272    void printAddr(Addr a);
273
274    /**
275     * Finish a DTB translation.
276     * @param state The DTB translation state.
277     */
278    void finishTranslation(WholeTranslationState *state);
279
280  private:
281
282    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
283    FetchEvent fetchEvent;
284
285    struct IprEvent : Event {
286        Packet *pkt;
287        TimingSimpleCPU *cpu;
288        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
289        virtual void process();
290        virtual const char *description() const;
291    };
292
293    void completeDrain();
294};
295
296#endif // __CPU_SIMPLE_TIMING_HH__
297