timing.hh revision 5177:4307a768e10e
12330SN/A/* 22330SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Steve Reinhardt 292330SN/A */ 302330SN/A 312683Sktlim@umich.edu#ifndef __CPU_SIMPLE_TIMING_HH__ 322683Sktlim@umich.edu#define __CPU_SIMPLE_TIMING_HH__ 332315SN/A 342315SN/A#include "cpu/simple/base.hh" 352683Sktlim@umich.edu 362680SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 372315SN/A{ 382315SN/A public: 392330SN/A 402330SN/A struct Params : public BaseSimpleCPU::Params { 412330SN/A }; 422315SN/A 432350SN/A TimingSimpleCPU(Params *params); 442680SN/A virtual ~TimingSimpleCPU(); 452680SN/A 462683Sktlim@umich.edu virtual void init(); 472683Sktlim@umich.edu 482683Sktlim@umich.edu public: 492683Sktlim@umich.edu // 502350SN/A enum Status { 512680SN/A Idle, 522680SN/A Running, 532315SN/A IcacheRetry, 542315SN/A IcacheWaitResponse, 552680SN/A IcacheWaitSwitch, 562683Sktlim@umich.edu DcacheRetry, 572683Sktlim@umich.edu DcacheWaitResponse, 582330SN/A DcacheWaitSwitch, 592315SN/A SwitchedOut 602315SN/A }; 612315SN/A 622683Sktlim@umich.edu protected: 632683Sktlim@umich.edu Status _status; 642680SN/A 652683Sktlim@umich.edu Status status() const { return _status; } 662683Sktlim@umich.edu 672683Sktlim@umich.edu Event *drainEvent; 682683Sktlim@umich.edu 692683Sktlim@umich.edu private: 702315SN/A 712315SN/A class CpuPort : public Port 722315SN/A { 732315SN/A protected: 742680SN/A TimingSimpleCPU *cpu; 752315SN/A Tick lat; 762315SN/A 772315SN/A public: 782680SN/A 792680SN/A CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 802315SN/A : Port(_name, _cpu), cpu(_cpu), lat(_lat) 812315SN/A { } 822680SN/A 832315SN/A bool snoopRangeSent; 842315SN/A 852680SN/A protected: 862315SN/A 872680SN/A virtual Tick recvAtomic(PacketPtr pkt); 882315SN/A 892680SN/A virtual void recvFunctional(PacketPtr pkt); 902315SN/A 912680SN/A virtual void recvStatusChange(Status status); 922330SN/A 932680SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 942690Sktlim@umich.edu bool &snoop) 952690Sktlim@umich.edu { resp.clear(); snoop = false; } 962690Sktlim@umich.edu 972690Sktlim@umich.edu struct TickEvent : public Event 982690Sktlim@umich.edu { 992690Sktlim@umich.edu PacketPtr pkt; 1002690Sktlim@umich.edu TimingSimpleCPU *cpu; 1012315SN/A 1022690Sktlim@umich.edu TickEvent(TimingSimpleCPU *_cpu) 1032690Sktlim@umich.edu :Event(&mainEventQueue), cpu(_cpu) {} 1042680SN/A const char *description() { return "Timing CPU tick"; } 1052315SN/A void schedule(PacketPtr _pkt, Tick t); 1062315SN/A }; 1072680SN/A 1082315SN/A }; 1092315SN/A 1102330SN/A class IcachePort : public CpuPort 1112680SN/A { 1122680SN/A public: 1132330SN/A 1142315SN/A IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1152315SN/A : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1162315SN/A { } 1172680SN/A 1182315SN/A protected: 1192315SN/A 1202680SN/A virtual bool recvTiming(PacketPtr pkt); 1212315SN/A 1222315SN/A virtual void recvRetry(); 1232680SN/A 1242315SN/A struct ITickEvent : public TickEvent 1252315SN/A { 1262680SN/A 1272315SN/A ITickEvent(TimingSimpleCPU *_cpu) 1282315SN/A : TickEvent(_cpu) {} 1292680SN/A void process(); 1302315SN/A const char *description() { return "Timing CPU icache tick"; } 1312315SN/A }; 1322680SN/A 1332315SN/A ITickEvent tickEvent; 1342680SN/A 1352680SN/A }; 1362315SN/A 1372315SN/A class DcachePort : public CpuPort 1382680SN/A { 1392315SN/A public: 1402680SN/A 1412315SN/A DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1422680SN/A : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1432315SN/A { } 1442315SN/A 1452680SN/A virtual void setPeer(Port *port); 1462315SN/A 1472680SN/A protected: 1482680SN/A 1492315SN/A virtual bool recvTiming(PacketPtr pkt); 1502680SN/A 1512680SN/A virtual void recvRetry(); 1522315SN/A 1532315SN/A struct DTickEvent : public TickEvent 1542680SN/A { 1552315SN/A DTickEvent(TimingSimpleCPU *_cpu) 1562315SN/A : TickEvent(_cpu) {} 1572680SN/A void process(); 1582315SN/A const char *description() { return "Timing CPU dcache tick"; } 1592315SN/A }; 1602680SN/A 1612315SN/A DTickEvent tickEvent; 1622680SN/A 1632680SN/A }; 1642315SN/A 1652315SN/A IcachePort icachePort; 1662315SN/A DcachePort dcachePort; 1672315SN/A 1682680SN/A PacketPtr ifetch_pkt; 1692680SN/A PacketPtr dcache_pkt; 1702315SN/A 1712315SN/A Tick previousTick; 1722315SN/A 1732315SN/A public: 1742315SN/A 1752315SN/A virtual Port *getPort(const std::string &if_name, int idx = -1); 1762680SN/A 1772315SN/A virtual void serialize(std::ostream &os); 1782669SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1792680SN/A 1802315SN/A virtual unsigned int drain(Event *drain_event); 1812669SN/A virtual void resume(); 1822680SN/A 1832315SN/A void switchOut(); 1842669SN/A void takeOverFrom(BaseCPU *oldCPU); 1852680SN/A 1862669SN/A virtual void activateContext(int thread_num, int delay); 1872669SN/A virtual void suspendContext(int thread_num); 1882680SN/A 1892315SN/A template <class T> 1902315SN/A Fault read(Addr addr, T &data, unsigned flags); 1912315SN/A 1922680SN/A Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1932680SN/A int size, unsigned flags); 1942315SN/A 1952315SN/A template <class T> 1962669SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1972315SN/A 1982680SN/A Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1992680SN/A int size, unsigned flags); 2002315SN/A 2012315SN/A void fetch(); 2022669SN/A void completeIfetch(PacketPtr ); 2032315SN/A void completeDataAccess(PacketPtr ); 2042680SN/A void advanceInst(Fault fault); 2052680SN/A 2062315SN/A private: 2072315SN/A 2082669SN/A typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 2092315SN/A FetchEvent *fetchEvent; 2102680SN/A 2112680SN/A struct IprEvent : Event { 2122669SN/A Packet *pkt; 2132669SN/A TimingSimpleCPU *cpu; 2142669SN/A IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 2152669SN/A virtual void process(); 2162680SN/A virtual const char *description(); 2172680SN/A }; 2182315SN/A 2192315SN/A void completeDrain(); 2202680SN/A}; 2212315SN/A 2222315SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 2232315SN/A