timing.hh revision 2856 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36class TimingSimpleCPU : public BaseSimpleCPU
37{
38  public:
39
40    struct Params : public BaseSimpleCPU::Params {
41    };
42
43    TimingSimpleCPU(Params *params);
44    virtual ~TimingSimpleCPU();
45
46    virtual void init();
47
48  public:
49    //
50    enum Status {
51        Idle,
52        Running,
53        IcacheRetry,
54        IcacheWaitResponse,
55        IcacheWaitSwitch,
56        DcacheRetry,
57        DcacheWaitResponse,
58        DcacheWaitSwitch,
59        SwitchedOut
60    };
61
62  protected:
63    Status _status;
64
65    Status status() const { return _status; }
66
67    Event *drainEvent;
68
69  private:
70
71    class CpuPort : public Port
72    {
73      protected:
74        TimingSimpleCPU *cpu;
75
76      public:
77
78        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
79            : Port(_name), cpu(_cpu)
80        { }
81
82      protected:
83
84        virtual Tick recvAtomic(Packet *pkt);
85
86        virtual void recvFunctional(Packet *pkt);
87
88        virtual void recvStatusChange(Status status);
89
90        virtual void getDeviceAddressRanges(AddrRangeList &resp,
91            AddrRangeList &snoop)
92        { resp.clear(); snoop.clear(); }
93    };
94
95    class IcachePort : public CpuPort
96    {
97      public:
98
99        IcachePort(TimingSimpleCPU *_cpu)
100            : CpuPort(_cpu->name() + "-iport", _cpu)
101        { }
102
103      protected:
104
105        virtual bool recvTiming(Packet *pkt);
106
107        virtual void recvRetry();
108    };
109
110    class DcachePort : public CpuPort
111    {
112      public:
113
114        DcachePort(TimingSimpleCPU *_cpu)
115            : CpuPort(_cpu->name() + "-dport", _cpu)
116        { }
117
118      protected:
119
120        virtual bool recvTiming(Packet *pkt);
121
122        virtual void recvRetry();
123    };
124
125    IcachePort icachePort;
126    DcachePort dcachePort;
127
128    Packet *ifetch_pkt;
129    Packet *dcache_pkt;
130
131  public:
132
133    virtual Port *getPort(const std::string &if_name, int idx = -1);
134
135    virtual void serialize(std::ostream &os);
136    virtual void unserialize(Checkpoint *cp, const std::string &section);
137
138    virtual bool drain(Event *drain_event);
139    virtual void resume();
140    virtual void setMemoryMode(State new_mode);
141
142    void switchOut();
143    void takeOverFrom(BaseCPU *oldCPU);
144
145    virtual void activateContext(int thread_num, int delay);
146    virtual void suspendContext(int thread_num);
147
148    template <class T>
149    Fault read(Addr addr, T &data, unsigned flags);
150
151    template <class T>
152    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
153
154    void fetch();
155    void completeIfetch(Packet *);
156    void completeDataAccess(Packet *);
157    void advanceInst(Fault fault);
158  private:
159    void completeDrain();
160};
161
162#endif // __CPU_SIMPLE_TIMING_HH__
163