timing.hh revision 9258
12SN/A/* 210911Sandreas.sandberg@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 310911Sandreas.sandberg@arm.com * All rights reserved. 410911Sandreas.sandberg@arm.com * 510911Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 610911Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 710911Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 810911Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 910911Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1010911Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1110911Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1210911Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1310911Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157534Ssteve.reinhardt@amd.com * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322SN/A#define __CPU_SIMPLE_TIMING_HH__ 332SN/A 342SN/A#include "cpu/simple/base.hh" 352SN/A#include "cpu/translation.hh" 362SN/A#include "params/TimingSimpleCPU.hh" 372SN/A 382SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 392SN/A{ 402665Ssaidi@eecs.umich.edu public: 412665Ssaidi@eecs.umich.edu 422665Ssaidi@eecs.umich.edu TimingSimpleCPU(TimingSimpleCPUParams * params); 432SN/A virtual ~TimingSimpleCPU(); 442SN/A 452SN/A virtual void init(); 462SN/A 472SN/A public: 482SN/A Event *drainEvent; 492SN/A 502SN/A private: 512SN/A 525491Sgblack@eecs.umich.edu /* 535491Sgblack@eecs.umich.edu * If an access needs to be broken into fragments, currently at most two, 542SN/A * the the following two classes are used as the sender state of the 555491Sgblack@eecs.umich.edu * packets so the CPU can keep track of everything. In the main packet 562SN/A * sender state, there's an array with a spot for each fragment. If a 572SN/A * fragment has already been accepted by the CPU, aka isn't waiting for 588737Skoansin.tan@gmail.com * a retry, it's pointer is NULL. After each fragment has successfully 594762Snate@binkert.org * been processed, the "outstanding" counter is decremented. Once the 609342SAndreas.Sandberg@arm.com * count is zero, the entire larger access is complete. 619356Snilay@cs.wisc.edu */ 6256SN/A class SplitMainSenderState : public Packet::SenderState 632SN/A { 642797Sktlim@umich.edu public: 652797Sktlim@umich.edu int outstanding; 6610023Smatt.horsnell@ARM.com PacketPtr fragments[2]; 679196SAndreas.Sandberg@arm.com 682SN/A int 692SN/A getPendingFragment() 702SN/A { 719196SAndreas.Sandberg@arm.com if (fragments[0]) { 729196SAndreas.Sandberg@arm.com return 0; 739196SAndreas.Sandberg@arm.com } else if (fragments[1]) { 749196SAndreas.Sandberg@arm.com return 1; 759196SAndreas.Sandberg@arm.com } else { 769196SAndreas.Sandberg@arm.com return -1; 779196SAndreas.Sandberg@arm.com } 789196SAndreas.Sandberg@arm.com } 799196SAndreas.Sandberg@arm.com }; 809196SAndreas.Sandberg@arm.com 819196SAndreas.Sandberg@arm.com class SplitFragmentSenderState : public Packet::SenderState 829196SAndreas.Sandberg@arm.com { 839196SAndreas.Sandberg@arm.com public: 849196SAndreas.Sandberg@arm.com SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 859196SAndreas.Sandberg@arm.com bigPkt(_bigPkt), index(_index) 869196SAndreas.Sandberg@arm.com {} 879196SAndreas.Sandberg@arm.com PacketPtr bigPkt; 889342SAndreas.Sandberg@arm.com int index; 899196SAndreas.Sandberg@arm.com 909196SAndreas.Sandberg@arm.com void 919196SAndreas.Sandberg@arm.com clearFromParent() 929196SAndreas.Sandberg@arm.com { 939196SAndreas.Sandberg@arm.com SplitMainSenderState * main_send_state = 949196SAndreas.Sandberg@arm.com dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 959196SAndreas.Sandberg@arm.com main_send_state->fragments[index] = NULL; 962SN/A } 979342SAndreas.Sandberg@arm.com }; 982SN/A 992SN/A class FetchTranslation : public BaseTLB::Translation 1002SN/A { 1012SN/A protected: 1029196SAndreas.Sandberg@arm.com TimingSimpleCPU *cpu; 1032SN/A 1042SN/A public: 10510023Smatt.horsnell@ARM.com FetchTranslation(TimingSimpleCPU *_cpu) 10610023Smatt.horsnell@ARM.com : cpu(_cpu) 10710023Smatt.horsnell@ARM.com {} 1084762Snate@binkert.org 1099196SAndreas.Sandberg@arm.com void 1104762Snate@binkert.org markDelayed() 1114762Snate@binkert.org { 1122SN/A assert(cpu->_status == Running); 1134762Snate@binkert.org cpu->_status = ITBWaitResponse; 1144762Snate@binkert.org } 1154762Snate@binkert.org 11610422Sandreas.hansson@arm.com void 1172SN/A finish(Fault fault, RequestPtr req, ThreadContext *tc, 1185034Smilesck@eecs.umich.edu BaseTLB::Mode mode) 1195034Smilesck@eecs.umich.edu { 1201553SN/A cpu->sendFetch(fault, req, tc); 121265SN/A } 1227532Ssteve.reinhardt@amd.com }; 1237532Ssteve.reinhardt@amd.com FetchTranslation fetchTranslation; 1247532Ssteve.reinhardt@amd.com 1257532Ssteve.reinhardt@amd.com void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read); 1267532Ssteve.reinhardt@amd.com void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, 1277532Ssteve.reinhardt@amd.com uint8_t *data, bool read); 128465SN/A 129465SN/A void translationFault(Fault fault); 1307532Ssteve.reinhardt@amd.com 1317532Ssteve.reinhardt@amd.com void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 1327532Ssteve.reinhardt@amd.com void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 1337532Ssteve.reinhardt@amd.com RequestPtr req1, RequestPtr req2, RequestPtr req, 1347532Ssteve.reinhardt@amd.com uint8_t *data, bool read); 1357532Ssteve.reinhardt@amd.com 1367532Ssteve.reinhardt@amd.com bool handleReadPacket(PacketPtr pkt); 1377532Ssteve.reinhardt@amd.com // This function always implicitly uses dcache_pkt. 1389196SAndreas.Sandberg@arm.com bool handleWritePacket(); 1399196SAndreas.Sandberg@arm.com 1407532Ssteve.reinhardt@amd.com /** 14110905Sandreas.sandberg@arm.com * A TimingCPUPort overrides the default behaviour of the 1427532Ssteve.reinhardt@amd.com * recvTiming and recvRetry and implements events for the 1437532Ssteve.reinhardt@amd.com * scheduling of handling of incoming packets in the following 1447532Ssteve.reinhardt@amd.com * cycle. 1457532Ssteve.reinhardt@amd.com */ 1467532Ssteve.reinhardt@amd.com class TimingCPUPort : public CpuPort 1477532Ssteve.reinhardt@amd.com { 1487532Ssteve.reinhardt@amd.com public: 1497532Ssteve.reinhardt@amd.com 1509196SAndreas.Sandberg@arm.com TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) 1519196SAndreas.Sandberg@arm.com : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this) 1529196SAndreas.Sandberg@arm.com { } 1532SN/A 1549196SAndreas.Sandberg@arm.com protected: 1559196SAndreas.Sandberg@arm.com 1569196SAndreas.Sandberg@arm.com /** 1579196SAndreas.Sandberg@arm.com * Snooping a coherence request, do nothing. 158330SN/A */ 1592SN/A virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1607532Ssteve.reinhardt@amd.com 16110023Smatt.horsnell@ARM.com TimingSimpleCPU* cpu; 16210023Smatt.horsnell@ARM.com 16310023Smatt.horsnell@ARM.com struct TickEvent : public Event 16410023Smatt.horsnell@ARM.com { 16510023Smatt.horsnell@ARM.com PacketPtr pkt; 16610023Smatt.horsnell@ARM.com TimingSimpleCPU *cpu; 16710023Smatt.horsnell@ARM.com 16810023Smatt.horsnell@ARM.com TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} 16910023Smatt.horsnell@ARM.com const char *description() const { return "Timing CPU tick"; } 17010023Smatt.horsnell@ARM.com void schedule(PacketPtr _pkt, Tick t); 17110023Smatt.horsnell@ARM.com }; 17210023Smatt.horsnell@ARM.com 17310023Smatt.horsnell@ARM.com EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; 17410023Smatt.horsnell@ARM.com }; 17510023Smatt.horsnell@ARM.com 1767532Ssteve.reinhardt@amd.com class IcachePort : public TimingCPUPort 1777532Ssteve.reinhardt@amd.com { 1787823Ssteve.reinhardt@amd.com public: 1797532Ssteve.reinhardt@amd.com 1807532Ssteve.reinhardt@amd.com IcachePort(TimingSimpleCPU *_cpu) 1817492Ssteve.reinhardt@amd.com : TimingCPUPort(_cpu->name() + ".icache_port", _cpu), 182330SN/A tickEvent(_cpu) 1839196SAndreas.Sandberg@arm.com { } 1849342SAndreas.Sandberg@arm.com 1859342SAndreas.Sandberg@arm.com protected: 1869342SAndreas.Sandberg@arm.com 1879342SAndreas.Sandberg@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1889342SAndreas.Sandberg@arm.com 1899342SAndreas.Sandberg@arm.com virtual void recvRetry(); 19010911Sandreas.sandberg@arm.com 19110911Sandreas.sandberg@arm.com struct ITickEvent : public TickEvent 19210911Sandreas.sandberg@arm.com { 19310911Sandreas.sandberg@arm.com 19410911Sandreas.sandberg@arm.com ITickEvent(TimingSimpleCPU *_cpu) 19510911Sandreas.sandberg@arm.com : TickEvent(_cpu) {} 19610911Sandreas.sandberg@arm.com void process(); 19710911Sandreas.sandberg@arm.com const char *description() const { return "Timing CPU icache tick"; } 19810911Sandreas.sandberg@arm.com }; 19910911Sandreas.sandberg@arm.com 20010911Sandreas.sandberg@arm.com ITickEvent tickEvent; 20110911Sandreas.sandberg@arm.com 20210911Sandreas.sandberg@arm.com }; 20310911Sandreas.sandberg@arm.com 20410911Sandreas.sandberg@arm.com class DcachePort : public TimingCPUPort 20510911Sandreas.sandberg@arm.com { 20610911Sandreas.sandberg@arm.com public: 20710911Sandreas.sandberg@arm.com 20810911Sandreas.sandberg@arm.com DcachePort(TimingSimpleCPU *_cpu) 20910911Sandreas.sandberg@arm.com : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu), 21010911Sandreas.sandberg@arm.com tickEvent(_cpu) 21110911Sandreas.sandberg@arm.com { } 21210905Sandreas.sandberg@arm.com 21310905Sandreas.sandberg@arm.com protected: 21410905Sandreas.sandberg@arm.com 21510905Sandreas.sandberg@arm.com virtual bool recvTimingResp(PacketPtr pkt); 2169342SAndreas.Sandberg@arm.com 2179196SAndreas.Sandberg@arm.com virtual void recvRetry(); 2189196SAndreas.Sandberg@arm.com 21910905Sandreas.sandberg@arm.com struct DTickEvent : public TickEvent 220938SN/A { 2211031SN/A DTickEvent(TimingSimpleCPU *_cpu) 2221031SN/A : TickEvent(_cpu) {} 2231031SN/A void process(); 2241031SN/A const char *description() const { return "Timing CPU dcache tick"; } 2251031SN/A }; 2261031SN/A 2275314Sstever@gmail.com DTickEvent tickEvent; 2285314Sstever@gmail.com 2295315Sstever@gmail.com }; 2305314Sstever@gmail.com 2315314Sstever@gmail.com IcachePort icachePort; 2325314Sstever@gmail.com DcachePort dcachePort; 2332SN/A 2342SN/A PacketPtr ifetch_pkt; 2359554Sandreas.hansson@arm.com PacketPtr dcache_pkt; 2369554Sandreas.hansson@arm.com 2379554Sandreas.hansson@arm.com Tick previousCycle; 2389554Sandreas.hansson@arm.com 2392SN/A protected: 240 241 /** Return a reference to the data port. */ 242 virtual CpuPort &getDataPort() { return dcachePort; } 243 244 /** Return a reference to the instruction port. */ 245 virtual CpuPort &getInstPort() { return icachePort; } 246 247 public: 248 249 virtual void serialize(std::ostream &os); 250 virtual void unserialize(Checkpoint *cp, const std::string §ion); 251 252 virtual unsigned int drain(Event *drain_event); 253 virtual void resume(); 254 255 void switchOut(); 256 void takeOverFrom(BaseCPU *oldCPU); 257 258 virtual void activateContext(ThreadID thread_num, Cycles delay); 259 virtual void suspendContext(ThreadID thread_num); 260 261 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 262 263 Fault writeMem(uint8_t *data, unsigned size, 264 Addr addr, unsigned flags, uint64_t *res); 265 266 void fetch(); 267 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 268 void completeIfetch(PacketPtr ); 269 void completeDataAccess(PacketPtr pkt); 270 void advanceInst(Fault fault); 271 272 /** This function is used by the page table walker to determine if it could 273 * translate the a pending request or if the underlying request has been 274 * squashed. This always returns false for the simple timing CPU as it never 275 * executes any instructions speculatively. 276 * @ return Is the current instruction squashed? 277 */ 278 bool isSquashed() const { return false; } 279 280 /** 281 * Print state of address in memory system via PrintReq (for 282 * debugging). 283 */ 284 void printAddr(Addr a); 285 286 /** 287 * Finish a DTB translation. 288 * @param state The DTB translation state. 289 */ 290 void finishTranslation(WholeTranslationState *state); 291 292 private: 293 294 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 295 FetchEvent fetchEvent; 296 297 struct IprEvent : Event { 298 Packet *pkt; 299 TimingSimpleCPU *cpu; 300 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 301 virtual void process(); 302 virtual const char *description() const; 303 }; 304 305 void completeDrain(); 306}; 307 308#endif // __CPU_SIMPLE_TIMING_HH__ 309