timing.hh revision 8707
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
322623SN/A#define __CPU_SIMPLE_TIMING_HH__
332623SN/A
342623SN/A#include "cpu/simple/base.hh"
356973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh"
365529Snate@binkert.org#include "params/TimingSimpleCPU.hh"
375529Snate@binkert.org
382623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
392623SN/A{
402623SN/A  public:
412623SN/A
425529Snate@binkert.org    TimingSimpleCPU(TimingSimpleCPUParams * params);
432623SN/A    virtual ~TimingSimpleCPU();
442623SN/A
452623SN/A    virtual void init();
462623SN/A
472623SN/A  public:
482839Sktlim@umich.edu    Event *drainEvent;
492798Sktlim@umich.edu
502623SN/A  private:
512623SN/A
525728Sgblack@eecs.umich.edu    /*
535728Sgblack@eecs.umich.edu     * If an access needs to be broken into fragments, currently at most two,
545728Sgblack@eecs.umich.edu     * the the following two classes are used as the sender state of the
555728Sgblack@eecs.umich.edu     * packets so the CPU can keep track of everything. In the main packet
565728Sgblack@eecs.umich.edu     * sender state, there's an array with a spot for each fragment. If a
575728Sgblack@eecs.umich.edu     * fragment has already been accepted by the CPU, aka isn't waiting for
585728Sgblack@eecs.umich.edu     * a retry, it's pointer is NULL. After each fragment has successfully
595728Sgblack@eecs.umich.edu     * been processed, the "outstanding" counter is decremented. Once the
605728Sgblack@eecs.umich.edu     * count is zero, the entire larger access is complete.
615728Sgblack@eecs.umich.edu     */
625728Sgblack@eecs.umich.edu    class SplitMainSenderState : public Packet::SenderState
635728Sgblack@eecs.umich.edu    {
645728Sgblack@eecs.umich.edu      public:
655728Sgblack@eecs.umich.edu        int outstanding;
665728Sgblack@eecs.umich.edu        PacketPtr fragments[2];
675728Sgblack@eecs.umich.edu
685728Sgblack@eecs.umich.edu        int
695728Sgblack@eecs.umich.edu        getPendingFragment()
705728Sgblack@eecs.umich.edu        {
715728Sgblack@eecs.umich.edu            if (fragments[0]) {
725728Sgblack@eecs.umich.edu                return 0;
735728Sgblack@eecs.umich.edu            } else if (fragments[1]) {
745728Sgblack@eecs.umich.edu                return 1;
755728Sgblack@eecs.umich.edu            } else {
765728Sgblack@eecs.umich.edu                return -1;
775728Sgblack@eecs.umich.edu            }
785728Sgblack@eecs.umich.edu        }
795728Sgblack@eecs.umich.edu    };
805728Sgblack@eecs.umich.edu
815728Sgblack@eecs.umich.edu    class SplitFragmentSenderState : public Packet::SenderState
825728Sgblack@eecs.umich.edu    {
835728Sgblack@eecs.umich.edu      public:
845728Sgblack@eecs.umich.edu        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
855728Sgblack@eecs.umich.edu            bigPkt(_bigPkt), index(_index)
865728Sgblack@eecs.umich.edu        {}
875728Sgblack@eecs.umich.edu        PacketPtr bigPkt;
885728Sgblack@eecs.umich.edu        int index;
895728Sgblack@eecs.umich.edu
905728Sgblack@eecs.umich.edu        void
915728Sgblack@eecs.umich.edu        clearFromParent()
925728Sgblack@eecs.umich.edu        {
935728Sgblack@eecs.umich.edu            SplitMainSenderState * main_send_state =
945728Sgblack@eecs.umich.edu                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
955728Sgblack@eecs.umich.edu            main_send_state->fragments[index] = NULL;
965728Sgblack@eecs.umich.edu        }
975728Sgblack@eecs.umich.edu    };
985728Sgblack@eecs.umich.edu
995894Sgblack@eecs.umich.edu    class FetchTranslation : public BaseTLB::Translation
1005894Sgblack@eecs.umich.edu    {
1015894Sgblack@eecs.umich.edu      protected:
1025894Sgblack@eecs.umich.edu        TimingSimpleCPU *cpu;
1035894Sgblack@eecs.umich.edu
1045894Sgblack@eecs.umich.edu      public:
1056023Snate@binkert.org        FetchTranslation(TimingSimpleCPU *_cpu)
1066023Snate@binkert.org            : cpu(_cpu)
1075894Sgblack@eecs.umich.edu        {}
1085894Sgblack@eecs.umich.edu
1096023Snate@binkert.org        void
1107944SGiacomo.Gabrielli@arm.com        markDelayed()
1117945SAli.Saidi@ARM.com        {
1127945SAli.Saidi@ARM.com            assert(cpu->_status == Running);
1137945SAli.Saidi@ARM.com            cpu->_status = ITBWaitResponse;
1147945SAli.Saidi@ARM.com        }
1157944SGiacomo.Gabrielli@arm.com
1167944SGiacomo.Gabrielli@arm.com        void
1176023Snate@binkert.org        finish(Fault fault, RequestPtr req, ThreadContext *tc,
1186023Snate@binkert.org               BaseTLB::Mode mode)
1195894Sgblack@eecs.umich.edu        {
1205894Sgblack@eecs.umich.edu            cpu->sendFetch(fault, req, tc);
1215894Sgblack@eecs.umich.edu        }
1225894Sgblack@eecs.umich.edu    };
1235894Sgblack@eecs.umich.edu    FetchTranslation fetchTranslation;
1245894Sgblack@eecs.umich.edu
1256973Stjones1@inf.ed.ac.uk    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
1266973Stjones1@inf.ed.ac.uk    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
1276973Stjones1@inf.ed.ac.uk                       uint8_t *data, bool read);
1285894Sgblack@eecs.umich.edu
1295894Sgblack@eecs.umich.edu    void translationFault(Fault fault);
1305894Sgblack@eecs.umich.edu
1315894Sgblack@eecs.umich.edu    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
1325894Sgblack@eecs.umich.edu    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
1335894Sgblack@eecs.umich.edu            RequestPtr req1, RequestPtr req2, RequestPtr req,
1345894Sgblack@eecs.umich.edu            uint8_t *data, bool read);
1355744Sgblack@eecs.umich.edu
1365728Sgblack@eecs.umich.edu    bool handleReadPacket(PacketPtr pkt);
1375728Sgblack@eecs.umich.edu    // This function always implicitly uses dcache_pkt.
1385728Sgblack@eecs.umich.edu    bool handleWritePacket();
1395728Sgblack@eecs.umich.edu
1408707Sandreas.hansson@arm.com    /**
1418707Sandreas.hansson@arm.com     * A TimingCPUPort overrides the default behaviour of the
1428707Sandreas.hansson@arm.com     * recvTiming and recvRetry and implements events for the
1438707Sandreas.hansson@arm.com     * scheduling of handling of incoming packets in the following
1448707Sandreas.hansson@arm.com     * cycle.
1458707Sandreas.hansson@arm.com     */
1468707Sandreas.hansson@arm.com    class TimingCPUPort : public CpuPort
1472623SN/A    {
1482623SN/A      public:
1492623SN/A
1508707Sandreas.hansson@arm.com        TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
1518707Sandreas.hansson@arm.com            : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
1522623SN/A        { }
1532623SN/A
1542623SN/A      protected:
1552623SN/A
1568707Sandreas.hansson@arm.com        TimingSimpleCPU* cpu;
1572948Ssaidi@eecs.umich.edu
1582948Ssaidi@eecs.umich.edu        struct TickEvent : public Event
1592948Ssaidi@eecs.umich.edu        {
1603349Sbinkertn@umich.edu            PacketPtr pkt;
1612948Ssaidi@eecs.umich.edu            TimingSimpleCPU *cpu;
1627745SAli.Saidi@ARM.com            CpuPort *port;
1632948Ssaidi@eecs.umich.edu
1648707Sandreas.hansson@arm.com            TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
1655336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU tick"; }
1663349Sbinkertn@umich.edu            void schedule(PacketPtr _pkt, Tick t);
1672948Ssaidi@eecs.umich.edu        };
1682948Ssaidi@eecs.umich.edu
1697745SAli.Saidi@ARM.com        EventWrapper<Port, &Port::sendRetry> retryEvent;
1702623SN/A    };
1712623SN/A
1728707Sandreas.hansson@arm.com    class IcachePort : public TimingCPUPort
1732623SN/A    {
1742623SN/A      public:
1752623SN/A
1768707Sandreas.hansson@arm.com        IcachePort(TimingSimpleCPU *_cpu)
1778707Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + "-iport", _cpu),
1788707Sandreas.hansson@arm.com              tickEvent(_cpu)
1792623SN/A        { }
1802623SN/A
1812623SN/A      protected:
1822623SN/A
1833349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
1842623SN/A
1852657Ssaidi@eecs.umich.edu        virtual void recvRetry();
1862948Ssaidi@eecs.umich.edu
1872948Ssaidi@eecs.umich.edu        struct ITickEvent : public TickEvent
1882948Ssaidi@eecs.umich.edu        {
1892948Ssaidi@eecs.umich.edu
1902948Ssaidi@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
1912948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
1922948Ssaidi@eecs.umich.edu            void process();
1935336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU icache tick"; }
1942948Ssaidi@eecs.umich.edu        };
1952948Ssaidi@eecs.umich.edu
1962948Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
1972948Ssaidi@eecs.umich.edu
1982623SN/A    };
1992623SN/A
2008707Sandreas.hansson@arm.com    class DcachePort : public TimingCPUPort
2012623SN/A    {
2022623SN/A      public:
2032623SN/A
2048707Sandreas.hansson@arm.com        DcachePort(TimingSimpleCPU *_cpu)
2058707Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
2062623SN/A        { }
2072623SN/A
2082623SN/A      protected:
2092623SN/A
2103349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
2112623SN/A
2122657Ssaidi@eecs.umich.edu        virtual void recvRetry();
2132948Ssaidi@eecs.umich.edu
2142948Ssaidi@eecs.umich.edu        struct DTickEvent : public TickEvent
2152948Ssaidi@eecs.umich.edu        {
2162948Ssaidi@eecs.umich.edu            DTickEvent(TimingSimpleCPU *_cpu)
2172948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2182948Ssaidi@eecs.umich.edu            void process();
2195336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU dcache tick"; }
2202948Ssaidi@eecs.umich.edu        };
2212948Ssaidi@eecs.umich.edu
2222948Ssaidi@eecs.umich.edu        DTickEvent tickEvent;
2232948Ssaidi@eecs.umich.edu
2242623SN/A    };
2252623SN/A
2262623SN/A    IcachePort icachePort;
2272623SN/A    DcachePort dcachePort;
2282623SN/A
2293349Sbinkertn@umich.edu    PacketPtr ifetch_pkt;
2303349Sbinkertn@umich.edu    PacketPtr dcache_pkt;
2312623SN/A
2323222Sktlim@umich.edu    Tick previousTick;
2333170Sstever@eecs.umich.edu
2342623SN/A  public:
2352623SN/A
2362856Srdreslin@umich.edu    virtual Port *getPort(const std::string &if_name, int idx = -1);
2372856Srdreslin@umich.edu
2382623SN/A    virtual void serialize(std::ostream &os);
2392623SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
2402623SN/A
2412901Ssaidi@eecs.umich.edu    virtual unsigned int drain(Event *drain_event);
2422798Sktlim@umich.edu    virtual void resume();
2432798Sktlim@umich.edu
2442798Sktlim@umich.edu    void switchOut();
2452623SN/A    void takeOverFrom(BaseCPU *oldCPU);
2462623SN/A
2472623SN/A    virtual void activateContext(int thread_num, int delay);
2482623SN/A    virtual void suspendContext(int thread_num);
2492623SN/A
2508444Sgblack@eecs.umich.edu    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
2517520Sgblack@eecs.umich.edu
2528444Sgblack@eecs.umich.edu    Fault writeMem(uint8_t *data, unsigned size,
2538444Sgblack@eecs.umich.edu                   Addr addr, unsigned flags, uint64_t *res);
2547520Sgblack@eecs.umich.edu
2552623SN/A    void fetch();
2565894Sgblack@eecs.umich.edu    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
2573349Sbinkertn@umich.edu    void completeIfetch(PacketPtr );
2585894Sgblack@eecs.umich.edu    void completeDataAccess(PacketPtr pkt);
2592644Sstever@eecs.umich.edu    void advanceInst(Fault fault);
2604471Sstever@eecs.umich.edu
2615315Sstever@gmail.com    /**
2625315Sstever@gmail.com     * Print state of address in memory system via PrintReq (for
2635315Sstever@gmail.com     * debugging).
2645315Sstever@gmail.com     */
2655315Sstever@gmail.com    void printAddr(Addr a);
2665315Sstever@gmail.com
2676973Stjones1@inf.ed.ac.uk    /**
2686973Stjones1@inf.ed.ac.uk     * Finish a DTB translation.
2696973Stjones1@inf.ed.ac.uk     * @param state The DTB translation state.
2706973Stjones1@inf.ed.ac.uk     */
2716973Stjones1@inf.ed.ac.uk    void finishTranslation(WholeTranslationState *state);
2726973Stjones1@inf.ed.ac.uk
2732798Sktlim@umich.edu  private:
2744471Sstever@eecs.umich.edu
2754471Sstever@eecs.umich.edu    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
2765710Scws3k@cs.virginia.edu    FetchEvent fetchEvent;
2774471Sstever@eecs.umich.edu
2785103Ssaidi@eecs.umich.edu    struct IprEvent : Event {
2795103Ssaidi@eecs.umich.edu        Packet *pkt;
2805103Ssaidi@eecs.umich.edu        TimingSimpleCPU *cpu;
2815103Ssaidi@eecs.umich.edu        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
2825103Ssaidi@eecs.umich.edu        virtual void process();
2835336Shines@cs.fsu.edu        virtual const char *description() const;
2845103Ssaidi@eecs.umich.edu    };
2855103Ssaidi@eecs.umich.edu
2862839Sktlim@umich.edu    void completeDrain();
2872623SN/A};
2882623SN/A
2892623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
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