timing.hh revision 8444
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 356973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 365529Snate@binkert.org#include "params/TimingSimpleCPU.hh" 375529Snate@binkert.org 382623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 392623SN/A{ 402623SN/A public: 412623SN/A 425529Snate@binkert.org TimingSimpleCPU(TimingSimpleCPUParams * params); 432623SN/A virtual ~TimingSimpleCPU(); 442623SN/A 452623SN/A virtual void init(); 462623SN/A 472623SN/A public: 482839Sktlim@umich.edu Event *drainEvent; 492798Sktlim@umich.edu 502623SN/A private: 512623SN/A 525728Sgblack@eecs.umich.edu /* 535728Sgblack@eecs.umich.edu * If an access needs to be broken into fragments, currently at most two, 545728Sgblack@eecs.umich.edu * the the following two classes are used as the sender state of the 555728Sgblack@eecs.umich.edu * packets so the CPU can keep track of everything. In the main packet 565728Sgblack@eecs.umich.edu * sender state, there's an array with a spot for each fragment. If a 575728Sgblack@eecs.umich.edu * fragment has already been accepted by the CPU, aka isn't waiting for 585728Sgblack@eecs.umich.edu * a retry, it's pointer is NULL. After each fragment has successfully 595728Sgblack@eecs.umich.edu * been processed, the "outstanding" counter is decremented. Once the 605728Sgblack@eecs.umich.edu * count is zero, the entire larger access is complete. 615728Sgblack@eecs.umich.edu */ 625728Sgblack@eecs.umich.edu class SplitMainSenderState : public Packet::SenderState 635728Sgblack@eecs.umich.edu { 645728Sgblack@eecs.umich.edu public: 655728Sgblack@eecs.umich.edu int outstanding; 665728Sgblack@eecs.umich.edu PacketPtr fragments[2]; 675728Sgblack@eecs.umich.edu 685728Sgblack@eecs.umich.edu int 695728Sgblack@eecs.umich.edu getPendingFragment() 705728Sgblack@eecs.umich.edu { 715728Sgblack@eecs.umich.edu if (fragments[0]) { 725728Sgblack@eecs.umich.edu return 0; 735728Sgblack@eecs.umich.edu } else if (fragments[1]) { 745728Sgblack@eecs.umich.edu return 1; 755728Sgblack@eecs.umich.edu } else { 765728Sgblack@eecs.umich.edu return -1; 775728Sgblack@eecs.umich.edu } 785728Sgblack@eecs.umich.edu } 795728Sgblack@eecs.umich.edu }; 805728Sgblack@eecs.umich.edu 815728Sgblack@eecs.umich.edu class SplitFragmentSenderState : public Packet::SenderState 825728Sgblack@eecs.umich.edu { 835728Sgblack@eecs.umich.edu public: 845728Sgblack@eecs.umich.edu SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 855728Sgblack@eecs.umich.edu bigPkt(_bigPkt), index(_index) 865728Sgblack@eecs.umich.edu {} 875728Sgblack@eecs.umich.edu PacketPtr bigPkt; 885728Sgblack@eecs.umich.edu int index; 895728Sgblack@eecs.umich.edu 905728Sgblack@eecs.umich.edu void 915728Sgblack@eecs.umich.edu clearFromParent() 925728Sgblack@eecs.umich.edu { 935728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 945728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 955728Sgblack@eecs.umich.edu main_send_state->fragments[index] = NULL; 965728Sgblack@eecs.umich.edu } 975728Sgblack@eecs.umich.edu }; 985728Sgblack@eecs.umich.edu 995894Sgblack@eecs.umich.edu class FetchTranslation : public BaseTLB::Translation 1005894Sgblack@eecs.umich.edu { 1015894Sgblack@eecs.umich.edu protected: 1025894Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1035894Sgblack@eecs.umich.edu 1045894Sgblack@eecs.umich.edu public: 1056023Snate@binkert.org FetchTranslation(TimingSimpleCPU *_cpu) 1066023Snate@binkert.org : cpu(_cpu) 1075894Sgblack@eecs.umich.edu {} 1085894Sgblack@eecs.umich.edu 1096023Snate@binkert.org void 1107944SGiacomo.Gabrielli@arm.com markDelayed() 1117945SAli.Saidi@ARM.com { 1127945SAli.Saidi@ARM.com assert(cpu->_status == Running); 1137945SAli.Saidi@ARM.com cpu->_status = ITBWaitResponse; 1147945SAli.Saidi@ARM.com } 1157944SGiacomo.Gabrielli@arm.com 1167944SGiacomo.Gabrielli@arm.com void 1176023Snate@binkert.org finish(Fault fault, RequestPtr req, ThreadContext *tc, 1186023Snate@binkert.org BaseTLB::Mode mode) 1195894Sgblack@eecs.umich.edu { 1205894Sgblack@eecs.umich.edu cpu->sendFetch(fault, req, tc); 1215894Sgblack@eecs.umich.edu } 1225894Sgblack@eecs.umich.edu }; 1235894Sgblack@eecs.umich.edu FetchTranslation fetchTranslation; 1245894Sgblack@eecs.umich.edu 1256973Stjones1@inf.ed.ac.uk void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read); 1266973Stjones1@inf.ed.ac.uk void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, 1276973Stjones1@inf.ed.ac.uk uint8_t *data, bool read); 1285894Sgblack@eecs.umich.edu 1295894Sgblack@eecs.umich.edu void translationFault(Fault fault); 1305894Sgblack@eecs.umich.edu 1315894Sgblack@eecs.umich.edu void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 1325894Sgblack@eecs.umich.edu void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 1335894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 1345894Sgblack@eecs.umich.edu uint8_t *data, bool read); 1355744Sgblack@eecs.umich.edu 1365728Sgblack@eecs.umich.edu bool handleReadPacket(PacketPtr pkt); 1375728Sgblack@eecs.umich.edu // This function always implicitly uses dcache_pkt. 1385728Sgblack@eecs.umich.edu bool handleWritePacket(); 1395728Sgblack@eecs.umich.edu 1402623SN/A class CpuPort : public Port 1412623SN/A { 1422623SN/A protected: 1432623SN/A TimingSimpleCPU *cpu; 1442948Ssaidi@eecs.umich.edu Tick lat; 1452623SN/A 1462623SN/A public: 1472623SN/A 1482948Ssaidi@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 1497745SAli.Saidi@ARM.com : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this) 1502623SN/A { } 1512623SN/A 1523647Srdreslin@umich.edu bool snoopRangeSent; 1533647Srdreslin@umich.edu 1542623SN/A protected: 1552623SN/A 1563349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1572623SN/A 1583349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1592623SN/A 1602623SN/A virtual void recvStatusChange(Status status); 1612623SN/A 1622623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1634475Sstever@eecs.umich.edu bool &snoop) 1644475Sstever@eecs.umich.edu { resp.clear(); snoop = false; } 1652948Ssaidi@eecs.umich.edu 1662948Ssaidi@eecs.umich.edu struct TickEvent : public Event 1672948Ssaidi@eecs.umich.edu { 1683349Sbinkertn@umich.edu PacketPtr pkt; 1692948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 1707745SAli.Saidi@ARM.com CpuPort *port; 1712948Ssaidi@eecs.umich.edu 1725606Snate@binkert.org TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} 1735336Shines@cs.fsu.edu const char *description() const { return "Timing CPU tick"; } 1743349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 1752948Ssaidi@eecs.umich.edu }; 1762948Ssaidi@eecs.umich.edu 1777745SAli.Saidi@ARM.com EventWrapper<Port, &Port::sendRetry> retryEvent; 1782623SN/A }; 1792623SN/A 1802623SN/A class IcachePort : public CpuPort 1812623SN/A { 1822623SN/A public: 1832623SN/A 1842948Ssaidi@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1852948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1862623SN/A { } 1872623SN/A 1882623SN/A protected: 1892623SN/A 1903349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1912623SN/A 1922657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1932948Ssaidi@eecs.umich.edu 1942948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 1952948Ssaidi@eecs.umich.edu { 1962948Ssaidi@eecs.umich.edu 1972948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 1982948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1992948Ssaidi@eecs.umich.edu void process(); 2005336Shines@cs.fsu.edu const char *description() const { return "Timing CPU icache tick"; } 2012948Ssaidi@eecs.umich.edu }; 2022948Ssaidi@eecs.umich.edu 2032948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 2042948Ssaidi@eecs.umich.edu 2052623SN/A }; 2062623SN/A 2072623SN/A class DcachePort : public CpuPort 2082623SN/A { 2092623SN/A public: 2102623SN/A 2112948Ssaidi@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 2122948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 2132623SN/A { } 2142623SN/A 2154192Sktlim@umich.edu virtual void setPeer(Port *port); 2164192Sktlim@umich.edu 2172623SN/A protected: 2182623SN/A 2193349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 2202623SN/A 2212657Ssaidi@eecs.umich.edu virtual void recvRetry(); 2222948Ssaidi@eecs.umich.edu 2232948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 2242948Ssaidi@eecs.umich.edu { 2252948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 2262948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 2272948Ssaidi@eecs.umich.edu void process(); 2285336Shines@cs.fsu.edu const char *description() const { return "Timing CPU dcache tick"; } 2292948Ssaidi@eecs.umich.edu }; 2302948Ssaidi@eecs.umich.edu 2312948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 2322948Ssaidi@eecs.umich.edu 2332623SN/A }; 2342623SN/A 2352623SN/A IcachePort icachePort; 2362623SN/A DcachePort dcachePort; 2372623SN/A 2383349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 2393349Sbinkertn@umich.edu PacketPtr dcache_pkt; 2402623SN/A 2413222Sktlim@umich.edu Tick previousTick; 2423170Sstever@eecs.umich.edu 2432623SN/A public: 2442623SN/A 2452856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2462856Srdreslin@umich.edu 2472623SN/A virtual void serialize(std::ostream &os); 2482623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2492623SN/A 2502901Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 2512798Sktlim@umich.edu virtual void resume(); 2522798Sktlim@umich.edu 2532798Sktlim@umich.edu void switchOut(); 2542623SN/A void takeOverFrom(BaseCPU *oldCPU); 2552623SN/A 2562623SN/A virtual void activateContext(int thread_num, int delay); 2572623SN/A virtual void suspendContext(int thread_num); 2582623SN/A 2598444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 2607520Sgblack@eecs.umich.edu 2618444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 2628444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 2637520Sgblack@eecs.umich.edu 2642623SN/A void fetch(); 2655894Sgblack@eecs.umich.edu void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 2663349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 2675894Sgblack@eecs.umich.edu void completeDataAccess(PacketPtr pkt); 2682644Sstever@eecs.umich.edu void advanceInst(Fault fault); 2694471Sstever@eecs.umich.edu 2705315Sstever@gmail.com /** 2715315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2725315Sstever@gmail.com * debugging). 2735315Sstever@gmail.com */ 2745315Sstever@gmail.com void printAddr(Addr a); 2755315Sstever@gmail.com 2766973Stjones1@inf.ed.ac.uk /** 2776973Stjones1@inf.ed.ac.uk * Finish a DTB translation. 2786973Stjones1@inf.ed.ac.uk * @param state The DTB translation state. 2796973Stjones1@inf.ed.ac.uk */ 2806973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 2816973Stjones1@inf.ed.ac.uk 2822798Sktlim@umich.edu private: 2834471Sstever@eecs.umich.edu 2844471Sstever@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 2855710Scws3k@cs.virginia.edu FetchEvent fetchEvent; 2864471Sstever@eecs.umich.edu 2875103Ssaidi@eecs.umich.edu struct IprEvent : Event { 2885103Ssaidi@eecs.umich.edu Packet *pkt; 2895103Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 2905103Ssaidi@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 2915103Ssaidi@eecs.umich.edu virtual void process(); 2925336Shines@cs.fsu.edu virtual const char *description() const; 2935103Ssaidi@eecs.umich.edu }; 2945103Ssaidi@eecs.umich.edu 2952839Sktlim@umich.edu void completeDrain(); 2962623SN/A}; 2972623SN/A 2982623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 299