timing.hh revision 6973
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
322623SN/A#define __CPU_SIMPLE_TIMING_HH__
332623SN/A
342623SN/A#include "cpu/simple/base.hh"
356973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh"
362623SN/A
375529Snate@binkert.org#include "params/TimingSimpleCPU.hh"
385529Snate@binkert.org
392623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
402623SN/A{
412623SN/A  public:
422623SN/A
435529Snate@binkert.org    TimingSimpleCPU(TimingSimpleCPUParams * params);
442623SN/A    virtual ~TimingSimpleCPU();
452623SN/A
462623SN/A    virtual void init();
472623SN/A
482623SN/A  public:
492839Sktlim@umich.edu    Event *drainEvent;
502798Sktlim@umich.edu
512623SN/A  private:
522623SN/A
535728Sgblack@eecs.umich.edu    /*
545728Sgblack@eecs.umich.edu     * If an access needs to be broken into fragments, currently at most two,
555728Sgblack@eecs.umich.edu     * the the following two classes are used as the sender state of the
565728Sgblack@eecs.umich.edu     * packets so the CPU can keep track of everything. In the main packet
575728Sgblack@eecs.umich.edu     * sender state, there's an array with a spot for each fragment. If a
585728Sgblack@eecs.umich.edu     * fragment has already been accepted by the CPU, aka isn't waiting for
595728Sgblack@eecs.umich.edu     * a retry, it's pointer is NULL. After each fragment has successfully
605728Sgblack@eecs.umich.edu     * been processed, the "outstanding" counter is decremented. Once the
615728Sgblack@eecs.umich.edu     * count is zero, the entire larger access is complete.
625728Sgblack@eecs.umich.edu     */
635728Sgblack@eecs.umich.edu    class SplitMainSenderState : public Packet::SenderState
645728Sgblack@eecs.umich.edu    {
655728Sgblack@eecs.umich.edu      public:
665728Sgblack@eecs.umich.edu        int outstanding;
675728Sgblack@eecs.umich.edu        PacketPtr fragments[2];
685728Sgblack@eecs.umich.edu
695728Sgblack@eecs.umich.edu        int
705728Sgblack@eecs.umich.edu        getPendingFragment()
715728Sgblack@eecs.umich.edu        {
725728Sgblack@eecs.umich.edu            if (fragments[0]) {
735728Sgblack@eecs.umich.edu                return 0;
745728Sgblack@eecs.umich.edu            } else if (fragments[1]) {
755728Sgblack@eecs.umich.edu                return 1;
765728Sgblack@eecs.umich.edu            } else {
775728Sgblack@eecs.umich.edu                return -1;
785728Sgblack@eecs.umich.edu            }
795728Sgblack@eecs.umich.edu        }
805728Sgblack@eecs.umich.edu    };
815728Sgblack@eecs.umich.edu
825728Sgblack@eecs.umich.edu    class SplitFragmentSenderState : public Packet::SenderState
835728Sgblack@eecs.umich.edu    {
845728Sgblack@eecs.umich.edu      public:
855728Sgblack@eecs.umich.edu        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
865728Sgblack@eecs.umich.edu            bigPkt(_bigPkt), index(_index)
875728Sgblack@eecs.umich.edu        {}
885728Sgblack@eecs.umich.edu        PacketPtr bigPkt;
895728Sgblack@eecs.umich.edu        int index;
905728Sgblack@eecs.umich.edu
915728Sgblack@eecs.umich.edu        void
925728Sgblack@eecs.umich.edu        clearFromParent()
935728Sgblack@eecs.umich.edu        {
945728Sgblack@eecs.umich.edu            SplitMainSenderState * main_send_state =
955728Sgblack@eecs.umich.edu                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
965728Sgblack@eecs.umich.edu            main_send_state->fragments[index] = NULL;
975728Sgblack@eecs.umich.edu        }
985728Sgblack@eecs.umich.edu    };
995728Sgblack@eecs.umich.edu
1005894Sgblack@eecs.umich.edu    class FetchTranslation : public BaseTLB::Translation
1015894Sgblack@eecs.umich.edu    {
1025894Sgblack@eecs.umich.edu      protected:
1035894Sgblack@eecs.umich.edu        TimingSimpleCPU *cpu;
1045894Sgblack@eecs.umich.edu
1055894Sgblack@eecs.umich.edu      public:
1066023Snate@binkert.org        FetchTranslation(TimingSimpleCPU *_cpu)
1076023Snate@binkert.org            : cpu(_cpu)
1085894Sgblack@eecs.umich.edu        {}
1095894Sgblack@eecs.umich.edu
1106023Snate@binkert.org        void
1116023Snate@binkert.org        finish(Fault fault, RequestPtr req, ThreadContext *tc,
1126023Snate@binkert.org               BaseTLB::Mode mode)
1135894Sgblack@eecs.umich.edu        {
1145894Sgblack@eecs.umich.edu            cpu->sendFetch(fault, req, tc);
1155894Sgblack@eecs.umich.edu        }
1165894Sgblack@eecs.umich.edu    };
1175894Sgblack@eecs.umich.edu    FetchTranslation fetchTranslation;
1185894Sgblack@eecs.umich.edu
1196973Stjones1@inf.ed.ac.uk    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
1206973Stjones1@inf.ed.ac.uk    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
1216973Stjones1@inf.ed.ac.uk                       uint8_t *data, bool read);
1225894Sgblack@eecs.umich.edu
1235894Sgblack@eecs.umich.edu    void translationFault(Fault fault);
1245894Sgblack@eecs.umich.edu
1255894Sgblack@eecs.umich.edu    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
1265894Sgblack@eecs.umich.edu    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
1275894Sgblack@eecs.umich.edu            RequestPtr req1, RequestPtr req2, RequestPtr req,
1285894Sgblack@eecs.umich.edu            uint8_t *data, bool read);
1295744Sgblack@eecs.umich.edu
1305728Sgblack@eecs.umich.edu    bool handleReadPacket(PacketPtr pkt);
1315728Sgblack@eecs.umich.edu    // This function always implicitly uses dcache_pkt.
1325728Sgblack@eecs.umich.edu    bool handleWritePacket();
1335728Sgblack@eecs.umich.edu
1342623SN/A    class CpuPort : public Port
1352623SN/A    {
1362623SN/A      protected:
1372623SN/A        TimingSimpleCPU *cpu;
1382948Ssaidi@eecs.umich.edu        Tick lat;
1392623SN/A
1402623SN/A      public:
1412623SN/A
1422948Ssaidi@eecs.umich.edu        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
1433401Sktlim@umich.edu            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
1442623SN/A        { }
1452623SN/A
1463647Srdreslin@umich.edu        bool snoopRangeSent;
1473647Srdreslin@umich.edu
1482623SN/A      protected:
1492623SN/A
1503349Sbinkertn@umich.edu        virtual Tick recvAtomic(PacketPtr pkt);
1512623SN/A
1523349Sbinkertn@umich.edu        virtual void recvFunctional(PacketPtr pkt);
1532623SN/A
1542623SN/A        virtual void recvStatusChange(Status status);
1552623SN/A
1562623SN/A        virtual void getDeviceAddressRanges(AddrRangeList &resp,
1574475Sstever@eecs.umich.edu                                            bool &snoop)
1584475Sstever@eecs.umich.edu        { resp.clear(); snoop = false; }
1592948Ssaidi@eecs.umich.edu
1602948Ssaidi@eecs.umich.edu        struct TickEvent : public Event
1612948Ssaidi@eecs.umich.edu        {
1623349Sbinkertn@umich.edu            PacketPtr pkt;
1632948Ssaidi@eecs.umich.edu            TimingSimpleCPU *cpu;
1642948Ssaidi@eecs.umich.edu
1655606Snate@binkert.org            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
1665336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU tick"; }
1673349Sbinkertn@umich.edu            void schedule(PacketPtr _pkt, Tick t);
1682948Ssaidi@eecs.umich.edu        };
1692948Ssaidi@eecs.umich.edu
1702623SN/A    };
1712623SN/A
1722623SN/A    class IcachePort : public CpuPort
1732623SN/A    {
1742623SN/A      public:
1752623SN/A
1762948Ssaidi@eecs.umich.edu        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
1772948Ssaidi@eecs.umich.edu            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
1782623SN/A        { }
1792623SN/A
1802623SN/A      protected:
1812623SN/A
1823349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
1832623SN/A
1842657Ssaidi@eecs.umich.edu        virtual void recvRetry();
1852948Ssaidi@eecs.umich.edu
1862948Ssaidi@eecs.umich.edu        struct ITickEvent : public TickEvent
1872948Ssaidi@eecs.umich.edu        {
1882948Ssaidi@eecs.umich.edu
1892948Ssaidi@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
1902948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
1912948Ssaidi@eecs.umich.edu            void process();
1925336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU icache tick"; }
1932948Ssaidi@eecs.umich.edu        };
1942948Ssaidi@eecs.umich.edu
1952948Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
1962948Ssaidi@eecs.umich.edu
1972623SN/A    };
1982623SN/A
1992623SN/A    class DcachePort : public CpuPort
2002623SN/A    {
2012623SN/A      public:
2022623SN/A
2032948Ssaidi@eecs.umich.edu        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
2042948Ssaidi@eecs.umich.edu            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
2052623SN/A        { }
2062623SN/A
2074192Sktlim@umich.edu        virtual void setPeer(Port *port);
2084192Sktlim@umich.edu
2092623SN/A      protected:
2102623SN/A
2113349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
2122623SN/A
2132657Ssaidi@eecs.umich.edu        virtual void recvRetry();
2142948Ssaidi@eecs.umich.edu
2152948Ssaidi@eecs.umich.edu        struct DTickEvent : public TickEvent
2162948Ssaidi@eecs.umich.edu        {
2172948Ssaidi@eecs.umich.edu            DTickEvent(TimingSimpleCPU *_cpu)
2182948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2192948Ssaidi@eecs.umich.edu            void process();
2205336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU dcache tick"; }
2212948Ssaidi@eecs.umich.edu        };
2222948Ssaidi@eecs.umich.edu
2232948Ssaidi@eecs.umich.edu        DTickEvent tickEvent;
2242948Ssaidi@eecs.umich.edu
2252623SN/A    };
2262623SN/A
2272623SN/A    IcachePort icachePort;
2282623SN/A    DcachePort dcachePort;
2292623SN/A
2303349Sbinkertn@umich.edu    PacketPtr ifetch_pkt;
2313349Sbinkertn@umich.edu    PacketPtr dcache_pkt;
2322623SN/A
2333222Sktlim@umich.edu    Tick previousTick;
2343170Sstever@eecs.umich.edu
2352623SN/A  public:
2362623SN/A
2372856Srdreslin@umich.edu    virtual Port *getPort(const std::string &if_name, int idx = -1);
2382856Srdreslin@umich.edu
2392623SN/A    virtual void serialize(std::ostream &os);
2402623SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
2412623SN/A
2422901Ssaidi@eecs.umich.edu    virtual unsigned int drain(Event *drain_event);
2432798Sktlim@umich.edu    virtual void resume();
2442798Sktlim@umich.edu
2452798Sktlim@umich.edu    void switchOut();
2462623SN/A    void takeOverFrom(BaseCPU *oldCPU);
2472623SN/A
2482623SN/A    virtual void activateContext(int thread_num, int delay);
2492623SN/A    virtual void suspendContext(int thread_num);
2502623SN/A
2512623SN/A    template <class T>
2522623SN/A    Fault read(Addr addr, T &data, unsigned flags);
2532623SN/A
2542623SN/A    template <class T>
2552623SN/A    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
2562623SN/A
2572623SN/A    void fetch();
2585894Sgblack@eecs.umich.edu    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
2593349Sbinkertn@umich.edu    void completeIfetch(PacketPtr );
2605894Sgblack@eecs.umich.edu    void completeDataAccess(PacketPtr pkt);
2612644Sstever@eecs.umich.edu    void advanceInst(Fault fault);
2624471Sstever@eecs.umich.edu
2635315Sstever@gmail.com    /**
2645315Sstever@gmail.com     * Print state of address in memory system via PrintReq (for
2655315Sstever@gmail.com     * debugging).
2665315Sstever@gmail.com     */
2675315Sstever@gmail.com    void printAddr(Addr a);
2685315Sstever@gmail.com
2696973Stjones1@inf.ed.ac.uk    /**
2706973Stjones1@inf.ed.ac.uk     * Finish a DTB translation.
2716973Stjones1@inf.ed.ac.uk     * @param state The DTB translation state.
2726973Stjones1@inf.ed.ac.uk     */
2736973Stjones1@inf.ed.ac.uk    void finishTranslation(WholeTranslationState *state);
2746973Stjones1@inf.ed.ac.uk
2752798Sktlim@umich.edu  private:
2764471Sstever@eecs.umich.edu
2774471Sstever@eecs.umich.edu    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
2785710Scws3k@cs.virginia.edu    FetchEvent fetchEvent;
2794471Sstever@eecs.umich.edu
2805103Ssaidi@eecs.umich.edu    struct IprEvent : Event {
2815103Ssaidi@eecs.umich.edu        Packet *pkt;
2825103Ssaidi@eecs.umich.edu        TimingSimpleCPU *cpu;
2835103Ssaidi@eecs.umich.edu        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
2845103Ssaidi@eecs.umich.edu        virtual void process();
2855336Shines@cs.fsu.edu        virtual const char *description() const;
2865103Ssaidi@eecs.umich.edu    };
2875103Ssaidi@eecs.umich.edu
2882839Sktlim@umich.edu    void completeDrain();
2892623SN/A};
2902623SN/A
2912623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
292