timing.hh revision 4475
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
322623SN/A#define __CPU_SIMPLE_TIMING_HH__
332623SN/A
342623SN/A#include "cpu/simple/base.hh"
352623SN/A
362623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
372623SN/A{
382623SN/A  public:
392623SN/A
402623SN/A    struct Params : public BaseSimpleCPU::Params {
412623SN/A    };
422623SN/A
432623SN/A    TimingSimpleCPU(Params *params);
442623SN/A    virtual ~TimingSimpleCPU();
452623SN/A
462623SN/A    virtual void init();
472623SN/A
482623SN/A  public:
492623SN/A    //
502623SN/A    enum Status {
512623SN/A        Idle,
522623SN/A        Running,
532623SN/A        IcacheRetry,
542623SN/A        IcacheWaitResponse,
552623SN/A        IcacheWaitSwitch,
562623SN/A        DcacheRetry,
572623SN/A        DcacheWaitResponse,
582623SN/A        DcacheWaitSwitch,
592623SN/A        SwitchedOut
602623SN/A    };
612623SN/A
622623SN/A  protected:
632623SN/A    Status _status;
642623SN/A
652623SN/A    Status status() const { return _status; }
662623SN/A
672839Sktlim@umich.edu    Event *drainEvent;
682798Sktlim@umich.edu
692623SN/A  private:
702623SN/A
712623SN/A    class CpuPort : public Port
722623SN/A    {
732623SN/A      protected:
742623SN/A        TimingSimpleCPU *cpu;
752948Ssaidi@eecs.umich.edu        Tick lat;
762623SN/A
772623SN/A      public:
782623SN/A
792948Ssaidi@eecs.umich.edu        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
803401Sktlim@umich.edu            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
812623SN/A        { }
822623SN/A
833647Srdreslin@umich.edu        bool snoopRangeSent;
843647Srdreslin@umich.edu
852623SN/A      protected:
862623SN/A
873349Sbinkertn@umich.edu        virtual Tick recvAtomic(PacketPtr pkt);
882623SN/A
893349Sbinkertn@umich.edu        virtual void recvFunctional(PacketPtr pkt);
902623SN/A
912623SN/A        virtual void recvStatusChange(Status status);
922623SN/A
932623SN/A        virtual void getDeviceAddressRanges(AddrRangeList &resp,
944475Sstever@eecs.umich.edu                                            bool &snoop)
954475Sstever@eecs.umich.edu        { resp.clear(); snoop = false; }
962948Ssaidi@eecs.umich.edu
972948Ssaidi@eecs.umich.edu        struct TickEvent : public Event
982948Ssaidi@eecs.umich.edu        {
993349Sbinkertn@umich.edu            PacketPtr pkt;
1002948Ssaidi@eecs.umich.edu            TimingSimpleCPU *cpu;
1012948Ssaidi@eecs.umich.edu
1022948Ssaidi@eecs.umich.edu            TickEvent(TimingSimpleCPU *_cpu)
1032948Ssaidi@eecs.umich.edu                :Event(&mainEventQueue), cpu(_cpu) {}
1042948Ssaidi@eecs.umich.edu            const char *description() { return "Timing CPU clock event"; }
1053349Sbinkertn@umich.edu            void schedule(PacketPtr _pkt, Tick t);
1062948Ssaidi@eecs.umich.edu        };
1072948Ssaidi@eecs.umich.edu
1082623SN/A    };
1092623SN/A
1102623SN/A    class IcachePort : public CpuPort
1112623SN/A    {
1122623SN/A      public:
1132623SN/A
1142948Ssaidi@eecs.umich.edu        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
1152948Ssaidi@eecs.umich.edu            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
1162623SN/A        { }
1172623SN/A
1182623SN/A      protected:
1192623SN/A
1203349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
1212623SN/A
1222657Ssaidi@eecs.umich.edu        virtual void recvRetry();
1232948Ssaidi@eecs.umich.edu
1242948Ssaidi@eecs.umich.edu        struct ITickEvent : public TickEvent
1252948Ssaidi@eecs.umich.edu        {
1262948Ssaidi@eecs.umich.edu
1272948Ssaidi@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
1282948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
1292948Ssaidi@eecs.umich.edu            void process();
1302948Ssaidi@eecs.umich.edu            const char *description() { return "Timing CPU clock event"; }
1312948Ssaidi@eecs.umich.edu        };
1322948Ssaidi@eecs.umich.edu
1332948Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
1342948Ssaidi@eecs.umich.edu
1352623SN/A    };
1362623SN/A
1372623SN/A    class DcachePort : public CpuPort
1382623SN/A    {
1392623SN/A      public:
1402623SN/A
1412948Ssaidi@eecs.umich.edu        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
1422948Ssaidi@eecs.umich.edu            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
1432623SN/A        { }
1442623SN/A
1454192Sktlim@umich.edu        virtual void setPeer(Port *port);
1464192Sktlim@umich.edu
1472623SN/A      protected:
1482623SN/A
1493349Sbinkertn@umich.edu        virtual bool recvTiming(PacketPtr pkt);
1502623SN/A
1512657Ssaidi@eecs.umich.edu        virtual void recvRetry();
1522948Ssaidi@eecs.umich.edu
1532948Ssaidi@eecs.umich.edu        struct DTickEvent : public TickEvent
1542948Ssaidi@eecs.umich.edu        {
1552948Ssaidi@eecs.umich.edu            DTickEvent(TimingSimpleCPU *_cpu)
1562948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
1572948Ssaidi@eecs.umich.edu            void process();
1582948Ssaidi@eecs.umich.edu            const char *description() { return "Timing CPU clock event"; }
1592948Ssaidi@eecs.umich.edu        };
1602948Ssaidi@eecs.umich.edu
1612948Ssaidi@eecs.umich.edu        DTickEvent tickEvent;
1622948Ssaidi@eecs.umich.edu
1632623SN/A    };
1642623SN/A
1652623SN/A    IcachePort icachePort;
1662623SN/A    DcachePort dcachePort;
1672623SN/A
1683349Sbinkertn@umich.edu    PacketPtr ifetch_pkt;
1693349Sbinkertn@umich.edu    PacketPtr dcache_pkt;
1702623SN/A
1713170Sstever@eecs.umich.edu    int cpu_id;
1723222Sktlim@umich.edu    Tick previousTick;
1733170Sstever@eecs.umich.edu
1742623SN/A  public:
1752623SN/A
1762856Srdreslin@umich.edu    virtual Port *getPort(const std::string &if_name, int idx = -1);
1772856Srdreslin@umich.edu
1782623SN/A    virtual void serialize(std::ostream &os);
1792623SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1802623SN/A
1812901Ssaidi@eecs.umich.edu    virtual unsigned int drain(Event *drain_event);
1822798Sktlim@umich.edu    virtual void resume();
1832798Sktlim@umich.edu
1842798Sktlim@umich.edu    void switchOut();
1852623SN/A    void takeOverFrom(BaseCPU *oldCPU);
1862623SN/A
1872623SN/A    virtual void activateContext(int thread_num, int delay);
1882623SN/A    virtual void suspendContext(int thread_num);
1892623SN/A
1902623SN/A    template <class T>
1912623SN/A    Fault read(Addr addr, T &data, unsigned flags);
1922623SN/A
1932623SN/A    template <class T>
1942623SN/A    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
1952623SN/A
1962623SN/A    void fetch();
1973349Sbinkertn@umich.edu    void completeIfetch(PacketPtr );
1983349Sbinkertn@umich.edu    void completeDataAccess(PacketPtr );
1992644Sstever@eecs.umich.edu    void advanceInst(Fault fault);
2004471Sstever@eecs.umich.edu
2012798Sktlim@umich.edu  private:
2024471Sstever@eecs.umich.edu
2034471Sstever@eecs.umich.edu    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
2044471Sstever@eecs.umich.edu    FetchEvent *fetchEvent;
2054471Sstever@eecs.umich.edu
2062839Sktlim@umich.edu    void completeDrain();
2072623SN/A};
2082623SN/A
2092623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
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