timing.hh revision 2644
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272623SN/A */
282623SN/A
292623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
302623SN/A#define __CPU_SIMPLE_TIMING_HH__
312623SN/A
322623SN/A#include "cpu/simple/base.hh"
332623SN/A
342623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
352623SN/A{
362623SN/A  public:
372623SN/A
382623SN/A    struct Params : public BaseSimpleCPU::Params {
392623SN/A    };
402623SN/A
412623SN/A    TimingSimpleCPU(Params *params);
422623SN/A    virtual ~TimingSimpleCPU();
432623SN/A
442623SN/A    virtual void init();
452623SN/A
462623SN/A  public:
472623SN/A    //
482623SN/A    enum Status {
492623SN/A        Idle,
502623SN/A        Running,
512623SN/A        IcacheRetry,
522623SN/A        IcacheWaitResponse,
532623SN/A        IcacheWaitSwitch,
542623SN/A        DcacheRetry,
552623SN/A        DcacheWaitResponse,
562623SN/A        DcacheWaitSwitch,
572623SN/A        SwitchedOut
582623SN/A    };
592623SN/A
602623SN/A  protected:
612623SN/A    Status _status;
622623SN/A
632623SN/A    Status status() const { return _status; }
642623SN/A
652623SN/A  private:
662623SN/A
672623SN/A    class CpuPort : public Port
682623SN/A    {
692623SN/A      protected:
702623SN/A        TimingSimpleCPU *cpu;
712623SN/A
722623SN/A      public:
732623SN/A
742640Sstever@eecs.umich.edu        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
752640Sstever@eecs.umich.edu            : Port(_name), cpu(_cpu)
762623SN/A        { }
772623SN/A
782623SN/A      protected:
792623SN/A
802630SN/A        virtual Tick recvAtomic(Packet *pkt);
812623SN/A
822630SN/A        virtual void recvFunctional(Packet *pkt);
832623SN/A
842623SN/A        virtual void recvStatusChange(Status status);
852623SN/A
862623SN/A        virtual void getDeviceAddressRanges(AddrRangeList &resp,
872623SN/A            AddrRangeList &snoop)
882623SN/A        { resp.clear(); snoop.clear(); }
892623SN/A    };
902623SN/A
912623SN/A    class IcachePort : public CpuPort
922623SN/A    {
932623SN/A      public:
942623SN/A
952623SN/A        IcachePort(TimingSimpleCPU *_cpu)
962640Sstever@eecs.umich.edu            : CpuPort(_cpu->name() + "-iport", _cpu)
972623SN/A        { }
982623SN/A
992623SN/A      protected:
1002623SN/A
1012630SN/A        virtual bool recvTiming(Packet *pkt);
1022623SN/A
1032623SN/A        virtual Packet *recvRetry();
1042623SN/A    };
1052623SN/A
1062623SN/A    class DcachePort : public CpuPort
1072623SN/A    {
1082623SN/A      public:
1092623SN/A
1102623SN/A        DcachePort(TimingSimpleCPU *_cpu)
1112640Sstever@eecs.umich.edu            : CpuPort(_cpu->name() + "-dport", _cpu)
1122623SN/A        { }
1132623SN/A
1142623SN/A      protected:
1152623SN/A
1162630SN/A        virtual bool recvTiming(Packet *pkt);
1172623SN/A
1182623SN/A        virtual Packet *recvRetry();
1192623SN/A    };
1202623SN/A
1212623SN/A    IcachePort icachePort;
1222623SN/A    DcachePort dcachePort;
1232623SN/A
1242623SN/A    Packet *ifetch_pkt;
1252623SN/A    Packet *dcache_pkt;
1262623SN/A
1272623SN/A  public:
1282623SN/A
1292623SN/A    virtual void serialize(std::ostream &os);
1302623SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1312623SN/A
1322623SN/A    void switchOut(Sampler *s);
1332623SN/A    void takeOverFrom(BaseCPU *oldCPU);
1342623SN/A
1352623SN/A    virtual void activateContext(int thread_num, int delay);
1362623SN/A    virtual void suspendContext(int thread_num);
1372623SN/A
1382623SN/A    template <class T>
1392623SN/A    Fault read(Addr addr, T &data, unsigned flags);
1402623SN/A
1412623SN/A    template <class T>
1422623SN/A    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
1432623SN/A
1442623SN/A    void fetch();
1452644Sstever@eecs.umich.edu    void completeIfetch(Packet *);
1462623SN/A    void completeDataAccess(Packet *);
1472644Sstever@eecs.umich.edu    void advanceInst(Fault fault);
1482623SN/A};
1492623SN/A
1502623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
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