timing.hh revision 11608
12623SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 39442SAndreas.Sandberg@ARM.com * All rights reserved 49442SAndreas.Sandberg@ARM.com * 59442SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69442SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79442SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89442SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99442SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109442SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119442SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129442SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139442SAndreas.Sandberg@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 442623SN/A#define __CPU_SIMPLE_TIMING_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 4711147Smitch.hayenga@arm.com#include "cpu/simple/exec_context.hh" 486973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 495529Snate@binkert.org#include "params/TimingSimpleCPU.hh" 505529Snate@binkert.org 512623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 522623SN/A{ 532623SN/A public: 542623SN/A 555529Snate@binkert.org TimingSimpleCPU(TimingSimpleCPUParams * params); 562623SN/A virtual ~TimingSimpleCPU(); 572623SN/A 5811169Sandreas.hansson@arm.com void init() override; 592623SN/A 602623SN/A private: 612623SN/A 625728Sgblack@eecs.umich.edu /* 635728Sgblack@eecs.umich.edu * If an access needs to be broken into fragments, currently at most two, 645728Sgblack@eecs.umich.edu * the the following two classes are used as the sender state of the 655728Sgblack@eecs.umich.edu * packets so the CPU can keep track of everything. In the main packet 665728Sgblack@eecs.umich.edu * sender state, there's an array with a spot for each fragment. If a 675728Sgblack@eecs.umich.edu * fragment has already been accepted by the CPU, aka isn't waiting for 685728Sgblack@eecs.umich.edu * a retry, it's pointer is NULL. After each fragment has successfully 695728Sgblack@eecs.umich.edu * been processed, the "outstanding" counter is decremented. Once the 705728Sgblack@eecs.umich.edu * count is zero, the entire larger access is complete. 715728Sgblack@eecs.umich.edu */ 725728Sgblack@eecs.umich.edu class SplitMainSenderState : public Packet::SenderState 735728Sgblack@eecs.umich.edu { 745728Sgblack@eecs.umich.edu public: 755728Sgblack@eecs.umich.edu int outstanding; 765728Sgblack@eecs.umich.edu PacketPtr fragments[2]; 775728Sgblack@eecs.umich.edu 785728Sgblack@eecs.umich.edu int 795728Sgblack@eecs.umich.edu getPendingFragment() 805728Sgblack@eecs.umich.edu { 815728Sgblack@eecs.umich.edu if (fragments[0]) { 825728Sgblack@eecs.umich.edu return 0; 835728Sgblack@eecs.umich.edu } else if (fragments[1]) { 845728Sgblack@eecs.umich.edu return 1; 855728Sgblack@eecs.umich.edu } else { 865728Sgblack@eecs.umich.edu return -1; 875728Sgblack@eecs.umich.edu } 885728Sgblack@eecs.umich.edu } 895728Sgblack@eecs.umich.edu }; 905728Sgblack@eecs.umich.edu 915728Sgblack@eecs.umich.edu class SplitFragmentSenderState : public Packet::SenderState 925728Sgblack@eecs.umich.edu { 935728Sgblack@eecs.umich.edu public: 945728Sgblack@eecs.umich.edu SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 955728Sgblack@eecs.umich.edu bigPkt(_bigPkt), index(_index) 965728Sgblack@eecs.umich.edu {} 975728Sgblack@eecs.umich.edu PacketPtr bigPkt; 985728Sgblack@eecs.umich.edu int index; 995728Sgblack@eecs.umich.edu 1005728Sgblack@eecs.umich.edu void 1015728Sgblack@eecs.umich.edu clearFromParent() 1025728Sgblack@eecs.umich.edu { 1035728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 1045728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 1055728Sgblack@eecs.umich.edu main_send_state->fragments[index] = NULL; 1065728Sgblack@eecs.umich.edu } 1075728Sgblack@eecs.umich.edu }; 1085728Sgblack@eecs.umich.edu 1095894Sgblack@eecs.umich.edu class FetchTranslation : public BaseTLB::Translation 1105894Sgblack@eecs.umich.edu { 1115894Sgblack@eecs.umich.edu protected: 1125894Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1135894Sgblack@eecs.umich.edu 1145894Sgblack@eecs.umich.edu public: 1156023Snate@binkert.org FetchTranslation(TimingSimpleCPU *_cpu) 1166023Snate@binkert.org : cpu(_cpu) 1175894Sgblack@eecs.umich.edu {} 1185894Sgblack@eecs.umich.edu 1196023Snate@binkert.org void 1207944SGiacomo.Gabrielli@arm.com markDelayed() 1217945SAli.Saidi@ARM.com { 1229342SAndreas.Sandberg@arm.com assert(cpu->_status == BaseSimpleCPU::Running); 1237945SAli.Saidi@ARM.com cpu->_status = ITBWaitResponse; 1247945SAli.Saidi@ARM.com } 1257944SGiacomo.Gabrielli@arm.com 1267944SGiacomo.Gabrielli@arm.com void 12710379Sandreas.hansson@arm.com finish(const Fault &fault, RequestPtr req, ThreadContext *tc, 1286023Snate@binkert.org BaseTLB::Mode mode) 1295894Sgblack@eecs.umich.edu { 1305894Sgblack@eecs.umich.edu cpu->sendFetch(fault, req, tc); 1315894Sgblack@eecs.umich.edu } 1325894Sgblack@eecs.umich.edu }; 1335894Sgblack@eecs.umich.edu FetchTranslation fetchTranslation; 1345894Sgblack@eecs.umich.edu 13511148Smitch.hayenga@arm.com void threadSnoop(PacketPtr pkt, ThreadID sender); 1366973Stjones1@inf.ed.ac.uk void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read); 1376973Stjones1@inf.ed.ac.uk void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, 1386973Stjones1@inf.ed.ac.uk uint8_t *data, bool read); 1395894Sgblack@eecs.umich.edu 14010379Sandreas.hansson@arm.com void translationFault(const Fault &fault); 1415894Sgblack@eecs.umich.edu 14210653Sandreas.hansson@arm.com PacketPtr buildPacket(RequestPtr req, bool read); 1435894Sgblack@eecs.umich.edu void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 1445894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 1455894Sgblack@eecs.umich.edu uint8_t *data, bool read); 1465744Sgblack@eecs.umich.edu 1475728Sgblack@eecs.umich.edu bool handleReadPacket(PacketPtr pkt); 1485728Sgblack@eecs.umich.edu // This function always implicitly uses dcache_pkt. 1495728Sgblack@eecs.umich.edu bool handleWritePacket(); 1505728Sgblack@eecs.umich.edu 1518707Sandreas.hansson@arm.com /** 1528707Sandreas.hansson@arm.com * A TimingCPUPort overrides the default behaviour of the 1538707Sandreas.hansson@arm.com * recvTiming and recvRetry and implements events for the 1548707Sandreas.hansson@arm.com * scheduling of handling of incoming packets in the following 1558707Sandreas.hansson@arm.com * cycle. 1568707Sandreas.hansson@arm.com */ 1579608Sandreas.hansson@arm.com class TimingCPUPort : public MasterPort 1582623SN/A { 1592623SN/A public: 1602623SN/A 1618707Sandreas.hansson@arm.com TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) 16210713Sandreas.hansson@arm.com : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this) 1632623SN/A { } 1642623SN/A 1652623SN/A protected: 1662623SN/A 1678707Sandreas.hansson@arm.com TimingSimpleCPU* cpu; 1682948Ssaidi@eecs.umich.edu 1692948Ssaidi@eecs.umich.edu struct TickEvent : public Event 1702948Ssaidi@eecs.umich.edu { 1713349Sbinkertn@umich.edu PacketPtr pkt; 1722948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 1732948Ssaidi@eecs.umich.edu 1748707Sandreas.hansson@arm.com TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} 1755336Shines@cs.fsu.edu const char *description() const { return "Timing CPU tick"; } 1763349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 1772948Ssaidi@eecs.umich.edu }; 1782948Ssaidi@eecs.umich.edu 17910713Sandreas.hansson@arm.com EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent; 1802623SN/A }; 1812623SN/A 1828707Sandreas.hansson@arm.com class IcachePort : public TimingCPUPort 1832623SN/A { 1842623SN/A public: 1852623SN/A 1868707Sandreas.hansson@arm.com IcachePort(TimingSimpleCPU *_cpu) 1879095Sandreas.hansson@arm.com : TimingCPUPort(_cpu->name() + ".icache_port", _cpu), 1888707Sandreas.hansson@arm.com tickEvent(_cpu) 1892623SN/A { } 1902623SN/A 1912623SN/A protected: 1922623SN/A 1938975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1942623SN/A 19510713Sandreas.hansson@arm.com virtual void recvReqRetry(); 1962948Ssaidi@eecs.umich.edu 1972948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 1982948Ssaidi@eecs.umich.edu { 1992948Ssaidi@eecs.umich.edu 2002948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 2012948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 2022948Ssaidi@eecs.umich.edu void process(); 2035336Shines@cs.fsu.edu const char *description() const { return "Timing CPU icache tick"; } 2042948Ssaidi@eecs.umich.edu }; 2052948Ssaidi@eecs.umich.edu 2062948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 2072948Ssaidi@eecs.umich.edu 2082623SN/A }; 2092623SN/A 2108707Sandreas.hansson@arm.com class DcachePort : public TimingCPUPort 2112623SN/A { 2122623SN/A public: 2132623SN/A 2148707Sandreas.hansson@arm.com DcachePort(TimingSimpleCPU *_cpu) 2159095Sandreas.hansson@arm.com : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu), 2169095Sandreas.hansson@arm.com tickEvent(_cpu) 21710030SAli.Saidi@ARM.com { 21810030SAli.Saidi@ARM.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 21910030SAli.Saidi@ARM.com } 2202623SN/A 22110030SAli.Saidi@ARM.com Addr cacheBlockMask; 2222623SN/A protected: 2232623SN/A 22410030SAli.Saidi@ARM.com /** Snoop a coherence request, we need to check if this causes 22510030SAli.Saidi@ARM.com * a wakeup event on a cpu that is monitoring an address 22610030SAli.Saidi@ARM.com */ 22710030SAli.Saidi@ARM.com virtual void recvTimingSnoopReq(PacketPtr pkt); 22810529Smorr@cs.wisc.edu virtual void recvFunctionalSnoop(PacketPtr pkt); 22910030SAli.Saidi@ARM.com 2308975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 2312623SN/A 23210713Sandreas.hansson@arm.com virtual void recvReqRetry(); 2332948Ssaidi@eecs.umich.edu 23410529Smorr@cs.wisc.edu virtual bool isSnooping() const { 23510529Smorr@cs.wisc.edu return true; 23610529Smorr@cs.wisc.edu } 23710529Smorr@cs.wisc.edu 2382948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 2392948Ssaidi@eecs.umich.edu { 2402948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 2412948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 2422948Ssaidi@eecs.umich.edu void process(); 2435336Shines@cs.fsu.edu const char *description() const { return "Timing CPU dcache tick"; } 2442948Ssaidi@eecs.umich.edu }; 2452948Ssaidi@eecs.umich.edu 2462948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 2472948Ssaidi@eecs.umich.edu 2482623SN/A }; 2492623SN/A 25010464SAndreas.Sandberg@ARM.com void updateCycleCounts(); 25110464SAndreas.Sandberg@ARM.com 2522623SN/A IcachePort icachePort; 2532623SN/A DcachePort dcachePort; 2542623SN/A 2553349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 2563349Sbinkertn@umich.edu PacketPtr dcache_pkt; 2572623SN/A 25810464SAndreas.Sandberg@ARM.com Cycles previousCycle; 2593170Sstever@eecs.umich.edu 2608850Sandreas.hansson@arm.com protected: 2618850Sandreas.hansson@arm.com 2628850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 26311169Sandreas.hansson@arm.com MasterPort &getDataPort() override { return dcachePort; } 2648850Sandreas.hansson@arm.com 2658850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 26611169Sandreas.hansson@arm.com MasterPort &getInstPort() override { return icachePort; } 2678850Sandreas.hansson@arm.com 2682623SN/A public: 2692623SN/A 27011168Sandreas.hansson@arm.com DrainState drain() override; 27111168Sandreas.hansson@arm.com void drainResume() override; 2722798Sktlim@umich.edu 27311169Sandreas.hansson@arm.com void switchOut() override; 27411169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 2752623SN/A 27611169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 2779523SAndreas.Sandberg@ARM.com 27811169Sandreas.hansson@arm.com void activateContext(ThreadID thread_num) override; 27911169Sandreas.hansson@arm.com void suspendContext(ThreadID thread_num) override; 2802623SN/A 28111169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 28211608Snikos.nikoleris@arm.com Request::Flags flags) override; 2837520Sgblack@eecs.umich.edu 28411608Snikos.nikoleris@arm.com Fault initiateMemRead(Addr addr, unsigned size, 28511608Snikos.nikoleris@arm.com Request::Flags flags) override; 28611303Ssteve.reinhardt@amd.com 2878444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 28811608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) override; 2897520Sgblack@eecs.umich.edu 2902623SN/A void fetch(); 29110379Sandreas.hansson@arm.com void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc); 2923349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 2935894Sgblack@eecs.umich.edu void completeDataAccess(PacketPtr pkt); 29410379Sandreas.hansson@arm.com void advanceInst(const Fault &fault); 2954471Sstever@eecs.umich.edu 2969258SAli.Saidi@ARM.com /** This function is used by the page table walker to determine if it could 2979258SAli.Saidi@ARM.com * translate the a pending request or if the underlying request has been 2989258SAli.Saidi@ARM.com * squashed. This always returns false for the simple timing CPU as it never 2999258SAli.Saidi@ARM.com * executes any instructions speculatively. 3009258SAli.Saidi@ARM.com * @ return Is the current instruction squashed? 3019258SAli.Saidi@ARM.com */ 3029258SAli.Saidi@ARM.com bool isSquashed() const { return false; } 3039258SAli.Saidi@ARM.com 3045315Sstever@gmail.com /** 3055315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 3065315Sstever@gmail.com * debugging). 3075315Sstever@gmail.com */ 3085315Sstever@gmail.com void printAddr(Addr a); 3095315Sstever@gmail.com 3106973Stjones1@inf.ed.ac.uk /** 3116973Stjones1@inf.ed.ac.uk * Finish a DTB translation. 3126973Stjones1@inf.ed.ac.uk * @param state The DTB translation state. 3136973Stjones1@inf.ed.ac.uk */ 3146973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3156973Stjones1@inf.ed.ac.uk 3162798Sktlim@umich.edu private: 3174471Sstever@eecs.umich.edu 3184471Sstever@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 3195710Scws3k@cs.virginia.edu FetchEvent fetchEvent; 3204471Sstever@eecs.umich.edu 3215103Ssaidi@eecs.umich.edu struct IprEvent : Event { 3225103Ssaidi@eecs.umich.edu Packet *pkt; 3235103Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 3245103Ssaidi@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 3255103Ssaidi@eecs.umich.edu virtual void process(); 3265336Shines@cs.fsu.edu virtual const char *description() const; 3275103Ssaidi@eecs.umich.edu }; 3285103Ssaidi@eecs.umich.edu 3299442SAndreas.Sandberg@ARM.com /** 3309442SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 3319442SAndreas.Sandberg@ARM.com * 3329442SAndreas.Sandberg@ARM.com * We need to drain if: 3339442SAndreas.Sandberg@ARM.com * <ul> 3349442SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 3359442SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 3369442SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 3379442SAndreas.Sandberg@ARM.com * 3389442SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 3399830Sandreas.hansson@arm.com * 3409830Sandreas.hansson@arm.com * <li>A fetch event is scheduled. Normally this would never be the 3419840Sandreas.hansson@arm.com * case with microPC() == 0, but right after a context is 3429840Sandreas.hansson@arm.com * activated it can happen. 3439442SAndreas.Sandberg@ARM.com * </ul> 3449442SAndreas.Sandberg@ARM.com */ 3459442SAndreas.Sandberg@ARM.com bool isDrained() { 34611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 34711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 34811147Smitch.hayenga@arm.com 34911147Smitch.hayenga@arm.com return thread->microPC() == 0 && !t_info.stayAtPC && 35011147Smitch.hayenga@arm.com !fetchEvent.scheduled(); 3519442SAndreas.Sandberg@ARM.com } 3529442SAndreas.Sandberg@ARM.com 3539442SAndreas.Sandberg@ARM.com /** 3549442SAndreas.Sandberg@ARM.com * Try to complete a drain request. 3559442SAndreas.Sandberg@ARM.com * 3569442SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 3579442SAndreas.Sandberg@ARM.com */ 3589442SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 3592623SN/A}; 3602623SN/A 3612623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 362