timing.hh revision 11303
12623SN/A/*
211147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited
39442SAndreas.Sandberg@ARM.com * All rights reserved
49442SAndreas.Sandberg@ARM.com *
59442SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69442SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79442SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89442SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99442SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109442SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119442SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129442SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139442SAndreas.Sandberg@ARM.com *
142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
152623SN/A * All rights reserved.
162623SN/A *
172623SN/A * Redistribution and use in source and binary forms, with or without
182623SN/A * modification, are permitted provided that the following conditions are
192623SN/A * met: redistributions of source code must retain the above copyright
202623SN/A * notice, this list of conditions and the following disclaimer;
212623SN/A * redistributions in binary form must reproduce the above copyright
222623SN/A * notice, this list of conditions and the following disclaimer in the
232623SN/A * documentation and/or other materials provided with the distribution;
242623SN/A * neither the name of the copyright holders nor the names of its
252623SN/A * contributors may be used to endorse or promote products derived from
262623SN/A * this software without specific prior written permission.
272623SN/A *
282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
412623SN/A */
422623SN/A
432623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
442623SN/A#define __CPU_SIMPLE_TIMING_HH__
452623SN/A
462623SN/A#include "cpu/simple/base.hh"
4711147Smitch.hayenga@arm.com#include "cpu/simple/exec_context.hh"
486973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh"
495529Snate@binkert.org#include "params/TimingSimpleCPU.hh"
505529Snate@binkert.org
512623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
522623SN/A{
532623SN/A  public:
542623SN/A
555529Snate@binkert.org    TimingSimpleCPU(TimingSimpleCPUParams * params);
562623SN/A    virtual ~TimingSimpleCPU();
572623SN/A
5811169Sandreas.hansson@arm.com    void init() override;
592623SN/A
602623SN/A  private:
612623SN/A
625728Sgblack@eecs.umich.edu    /*
635728Sgblack@eecs.umich.edu     * If an access needs to be broken into fragments, currently at most two,
645728Sgblack@eecs.umich.edu     * the the following two classes are used as the sender state of the
655728Sgblack@eecs.umich.edu     * packets so the CPU can keep track of everything. In the main packet
665728Sgblack@eecs.umich.edu     * sender state, there's an array with a spot for each fragment. If a
675728Sgblack@eecs.umich.edu     * fragment has already been accepted by the CPU, aka isn't waiting for
685728Sgblack@eecs.umich.edu     * a retry, it's pointer is NULL. After each fragment has successfully
695728Sgblack@eecs.umich.edu     * been processed, the "outstanding" counter is decremented. Once the
705728Sgblack@eecs.umich.edu     * count is zero, the entire larger access is complete.
715728Sgblack@eecs.umich.edu     */
725728Sgblack@eecs.umich.edu    class SplitMainSenderState : public Packet::SenderState
735728Sgblack@eecs.umich.edu    {
745728Sgblack@eecs.umich.edu      public:
755728Sgblack@eecs.umich.edu        int outstanding;
765728Sgblack@eecs.umich.edu        PacketPtr fragments[2];
775728Sgblack@eecs.umich.edu
785728Sgblack@eecs.umich.edu        int
795728Sgblack@eecs.umich.edu        getPendingFragment()
805728Sgblack@eecs.umich.edu        {
815728Sgblack@eecs.umich.edu            if (fragments[0]) {
825728Sgblack@eecs.umich.edu                return 0;
835728Sgblack@eecs.umich.edu            } else if (fragments[1]) {
845728Sgblack@eecs.umich.edu                return 1;
855728Sgblack@eecs.umich.edu            } else {
865728Sgblack@eecs.umich.edu                return -1;
875728Sgblack@eecs.umich.edu            }
885728Sgblack@eecs.umich.edu        }
895728Sgblack@eecs.umich.edu    };
905728Sgblack@eecs.umich.edu
915728Sgblack@eecs.umich.edu    class SplitFragmentSenderState : public Packet::SenderState
925728Sgblack@eecs.umich.edu    {
935728Sgblack@eecs.umich.edu      public:
945728Sgblack@eecs.umich.edu        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
955728Sgblack@eecs.umich.edu            bigPkt(_bigPkt), index(_index)
965728Sgblack@eecs.umich.edu        {}
975728Sgblack@eecs.umich.edu        PacketPtr bigPkt;
985728Sgblack@eecs.umich.edu        int index;
995728Sgblack@eecs.umich.edu
1005728Sgblack@eecs.umich.edu        void
1015728Sgblack@eecs.umich.edu        clearFromParent()
1025728Sgblack@eecs.umich.edu        {
1035728Sgblack@eecs.umich.edu            SplitMainSenderState * main_send_state =
1045728Sgblack@eecs.umich.edu                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
1055728Sgblack@eecs.umich.edu            main_send_state->fragments[index] = NULL;
1065728Sgblack@eecs.umich.edu        }
1075728Sgblack@eecs.umich.edu    };
1085728Sgblack@eecs.umich.edu
1095894Sgblack@eecs.umich.edu    class FetchTranslation : public BaseTLB::Translation
1105894Sgblack@eecs.umich.edu    {
1115894Sgblack@eecs.umich.edu      protected:
1125894Sgblack@eecs.umich.edu        TimingSimpleCPU *cpu;
1135894Sgblack@eecs.umich.edu
1145894Sgblack@eecs.umich.edu      public:
1156023Snate@binkert.org        FetchTranslation(TimingSimpleCPU *_cpu)
1166023Snate@binkert.org            : cpu(_cpu)
1175894Sgblack@eecs.umich.edu        {}
1185894Sgblack@eecs.umich.edu
1196023Snate@binkert.org        void
1207944SGiacomo.Gabrielli@arm.com        markDelayed()
1217945SAli.Saidi@ARM.com        {
1229342SAndreas.Sandberg@arm.com            assert(cpu->_status == BaseSimpleCPU::Running);
1237945SAli.Saidi@ARM.com            cpu->_status = ITBWaitResponse;
1247945SAli.Saidi@ARM.com        }
1257944SGiacomo.Gabrielli@arm.com
1267944SGiacomo.Gabrielli@arm.com        void
12710379Sandreas.hansson@arm.com        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
1286023Snate@binkert.org               BaseTLB::Mode mode)
1295894Sgblack@eecs.umich.edu        {
1305894Sgblack@eecs.umich.edu            cpu->sendFetch(fault, req, tc);
1315894Sgblack@eecs.umich.edu        }
1325894Sgblack@eecs.umich.edu    };
1335894Sgblack@eecs.umich.edu    FetchTranslation fetchTranslation;
1345894Sgblack@eecs.umich.edu
13511148Smitch.hayenga@arm.com    void threadSnoop(PacketPtr pkt, ThreadID sender);
1366973Stjones1@inf.ed.ac.uk    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
1376973Stjones1@inf.ed.ac.uk    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
1386973Stjones1@inf.ed.ac.uk                       uint8_t *data, bool read);
1395894Sgblack@eecs.umich.edu
14010379Sandreas.hansson@arm.com    void translationFault(const Fault &fault);
1415894Sgblack@eecs.umich.edu
14210653Sandreas.hansson@arm.com    PacketPtr buildPacket(RequestPtr req, bool read);
1435894Sgblack@eecs.umich.edu    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
1445894Sgblack@eecs.umich.edu            RequestPtr req1, RequestPtr req2, RequestPtr req,
1455894Sgblack@eecs.umich.edu            uint8_t *data, bool read);
1465744Sgblack@eecs.umich.edu
1475728Sgblack@eecs.umich.edu    bool handleReadPacket(PacketPtr pkt);
1485728Sgblack@eecs.umich.edu    // This function always implicitly uses dcache_pkt.
1495728Sgblack@eecs.umich.edu    bool handleWritePacket();
1505728Sgblack@eecs.umich.edu
1518707Sandreas.hansson@arm.com    /**
1528707Sandreas.hansson@arm.com     * A TimingCPUPort overrides the default behaviour of the
1538707Sandreas.hansson@arm.com     * recvTiming and recvRetry and implements events for the
1548707Sandreas.hansson@arm.com     * scheduling of handling of incoming packets in the following
1558707Sandreas.hansson@arm.com     * cycle.
1568707Sandreas.hansson@arm.com     */
1579608Sandreas.hansson@arm.com    class TimingCPUPort : public MasterPort
1582623SN/A    {
1592623SN/A      public:
1602623SN/A
1618707Sandreas.hansson@arm.com        TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
16210713Sandreas.hansson@arm.com            : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
1632623SN/A        { }
1642623SN/A
1652623SN/A      protected:
1662623SN/A
1678948Sandreas.hansson@arm.com        /**
1688948Sandreas.hansson@arm.com         * Snooping a coherence request, do nothing.
1698948Sandreas.hansson@arm.com         */
17010030SAli.Saidi@ARM.com        virtual void recvTimingSnoopReq(PacketPtr pkt) {}
1718948Sandreas.hansson@arm.com
1728707Sandreas.hansson@arm.com        TimingSimpleCPU* cpu;
1732948Ssaidi@eecs.umich.edu
1742948Ssaidi@eecs.umich.edu        struct TickEvent : public Event
1752948Ssaidi@eecs.umich.edu        {
1763349Sbinkertn@umich.edu            PacketPtr pkt;
1772948Ssaidi@eecs.umich.edu            TimingSimpleCPU *cpu;
1782948Ssaidi@eecs.umich.edu
1798707Sandreas.hansson@arm.com            TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
1805336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU tick"; }
1813349Sbinkertn@umich.edu            void schedule(PacketPtr _pkt, Tick t);
1822948Ssaidi@eecs.umich.edu        };
1832948Ssaidi@eecs.umich.edu
18410713Sandreas.hansson@arm.com        EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
1852623SN/A    };
1862623SN/A
1878707Sandreas.hansson@arm.com    class IcachePort : public TimingCPUPort
1882623SN/A    {
1892623SN/A      public:
1902623SN/A
1918707Sandreas.hansson@arm.com        IcachePort(TimingSimpleCPU *_cpu)
1929095Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
1938707Sandreas.hansson@arm.com              tickEvent(_cpu)
1942623SN/A        { }
1952623SN/A
1962623SN/A      protected:
1972623SN/A
1988975Sandreas.hansson@arm.com        virtual bool recvTimingResp(PacketPtr pkt);
1992623SN/A
20010713Sandreas.hansson@arm.com        virtual void recvReqRetry();
2012948Ssaidi@eecs.umich.edu
2022948Ssaidi@eecs.umich.edu        struct ITickEvent : public TickEvent
2032948Ssaidi@eecs.umich.edu        {
2042948Ssaidi@eecs.umich.edu
2052948Ssaidi@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
2062948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2072948Ssaidi@eecs.umich.edu            void process();
2085336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU icache tick"; }
2092948Ssaidi@eecs.umich.edu        };
2102948Ssaidi@eecs.umich.edu
2112948Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
2122948Ssaidi@eecs.umich.edu
2132623SN/A    };
2142623SN/A
2158707Sandreas.hansson@arm.com    class DcachePort : public TimingCPUPort
2162623SN/A    {
2172623SN/A      public:
2182623SN/A
2198707Sandreas.hansson@arm.com        DcachePort(TimingSimpleCPU *_cpu)
2209095Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
2219095Sandreas.hansson@arm.com              tickEvent(_cpu)
22210030SAli.Saidi@ARM.com        {
22310030SAli.Saidi@ARM.com           cacheBlockMask = ~(cpu->cacheLineSize() - 1);
22410030SAli.Saidi@ARM.com        }
2252623SN/A
22610030SAli.Saidi@ARM.com        Addr cacheBlockMask;
2272623SN/A      protected:
2282623SN/A
22910030SAli.Saidi@ARM.com        /** Snoop a coherence request, we need to check if this causes
23010030SAli.Saidi@ARM.com         * a wakeup event on a cpu that is monitoring an address
23110030SAli.Saidi@ARM.com         */
23210030SAli.Saidi@ARM.com        virtual void recvTimingSnoopReq(PacketPtr pkt);
23310529Smorr@cs.wisc.edu        virtual void recvFunctionalSnoop(PacketPtr pkt);
23410030SAli.Saidi@ARM.com
2358975Sandreas.hansson@arm.com        virtual bool recvTimingResp(PacketPtr pkt);
2362623SN/A
23710713Sandreas.hansson@arm.com        virtual void recvReqRetry();
2382948Ssaidi@eecs.umich.edu
23910529Smorr@cs.wisc.edu        virtual bool isSnooping() const {
24010529Smorr@cs.wisc.edu            return true;
24110529Smorr@cs.wisc.edu        }
24210529Smorr@cs.wisc.edu
2432948Ssaidi@eecs.umich.edu        struct DTickEvent : public TickEvent
2442948Ssaidi@eecs.umich.edu        {
2452948Ssaidi@eecs.umich.edu            DTickEvent(TimingSimpleCPU *_cpu)
2462948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2472948Ssaidi@eecs.umich.edu            void process();
2485336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU dcache tick"; }
2492948Ssaidi@eecs.umich.edu        };
2502948Ssaidi@eecs.umich.edu
2512948Ssaidi@eecs.umich.edu        DTickEvent tickEvent;
2522948Ssaidi@eecs.umich.edu
2532623SN/A    };
2542623SN/A
25510464SAndreas.Sandberg@ARM.com    void updateCycleCounts();
25610464SAndreas.Sandberg@ARM.com
2572623SN/A    IcachePort icachePort;
2582623SN/A    DcachePort dcachePort;
2592623SN/A
2603349Sbinkertn@umich.edu    PacketPtr ifetch_pkt;
2613349Sbinkertn@umich.edu    PacketPtr dcache_pkt;
2622623SN/A
26310464SAndreas.Sandberg@ARM.com    Cycles previousCycle;
2643170Sstever@eecs.umich.edu
2658850Sandreas.hansson@arm.com  protected:
2668850Sandreas.hansson@arm.com
2678850Sandreas.hansson@arm.com     /** Return a reference to the data port. */
26811169Sandreas.hansson@arm.com    MasterPort &getDataPort() override { return dcachePort; }
2698850Sandreas.hansson@arm.com
2708850Sandreas.hansson@arm.com    /** Return a reference to the instruction port. */
27111169Sandreas.hansson@arm.com    MasterPort &getInstPort() override { return icachePort; }
2728850Sandreas.hansson@arm.com
2732623SN/A  public:
2742623SN/A
27511168Sandreas.hansson@arm.com    DrainState drain() override;
27611168Sandreas.hansson@arm.com    void drainResume() override;
2772798Sktlim@umich.edu
27811169Sandreas.hansson@arm.com    void switchOut() override;
27911169Sandreas.hansson@arm.com    void takeOverFrom(BaseCPU *oldCPU) override;
2802623SN/A
28111169Sandreas.hansson@arm.com    void verifyMemoryMode() const override;
2829523SAndreas.Sandberg@ARM.com
28311169Sandreas.hansson@arm.com    void activateContext(ThreadID thread_num) override;
28411169Sandreas.hansson@arm.com    void suspendContext(ThreadID thread_num) override;
2852623SN/A
28611169Sandreas.hansson@arm.com    Fault readMem(Addr addr, uint8_t *data, unsigned size,
28711169Sandreas.hansson@arm.com                  unsigned flags) override;
2887520Sgblack@eecs.umich.edu
28911303Ssteve.reinhardt@amd.com    Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) override;
29011303Ssteve.reinhardt@amd.com
2918444Sgblack@eecs.umich.edu    Fault writeMem(uint8_t *data, unsigned size,
29211169Sandreas.hansson@arm.com                   Addr addr, unsigned flags, uint64_t *res) override;
2937520Sgblack@eecs.umich.edu
2942623SN/A    void fetch();
29510379Sandreas.hansson@arm.com    void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
2963349Sbinkertn@umich.edu    void completeIfetch(PacketPtr );
2975894Sgblack@eecs.umich.edu    void completeDataAccess(PacketPtr pkt);
29810379Sandreas.hansson@arm.com    void advanceInst(const Fault &fault);
2994471Sstever@eecs.umich.edu
3009258SAli.Saidi@ARM.com    /** This function is used by the page table walker to determine if it could
3019258SAli.Saidi@ARM.com     * translate the a pending request or if the underlying request has been
3029258SAli.Saidi@ARM.com     * squashed. This always returns false for the simple timing CPU as it never
3039258SAli.Saidi@ARM.com     * executes any instructions speculatively.
3049258SAli.Saidi@ARM.com     * @ return Is the current instruction squashed?
3059258SAli.Saidi@ARM.com     */
3069258SAli.Saidi@ARM.com    bool isSquashed() const { return false; }
3079258SAli.Saidi@ARM.com
3085315Sstever@gmail.com    /**
3095315Sstever@gmail.com     * Print state of address in memory system via PrintReq (for
3105315Sstever@gmail.com     * debugging).
3115315Sstever@gmail.com     */
3125315Sstever@gmail.com    void printAddr(Addr a);
3135315Sstever@gmail.com
3146973Stjones1@inf.ed.ac.uk    /**
3156973Stjones1@inf.ed.ac.uk     * Finish a DTB translation.
3166973Stjones1@inf.ed.ac.uk     * @param state The DTB translation state.
3176973Stjones1@inf.ed.ac.uk     */
3186973Stjones1@inf.ed.ac.uk    void finishTranslation(WholeTranslationState *state);
3196973Stjones1@inf.ed.ac.uk
3202798Sktlim@umich.edu  private:
3214471Sstever@eecs.umich.edu
3224471Sstever@eecs.umich.edu    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
3235710Scws3k@cs.virginia.edu    FetchEvent fetchEvent;
3244471Sstever@eecs.umich.edu
3255103Ssaidi@eecs.umich.edu    struct IprEvent : Event {
3265103Ssaidi@eecs.umich.edu        Packet *pkt;
3275103Ssaidi@eecs.umich.edu        TimingSimpleCPU *cpu;
3285103Ssaidi@eecs.umich.edu        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
3295103Ssaidi@eecs.umich.edu        virtual void process();
3305336Shines@cs.fsu.edu        virtual const char *description() const;
3315103Ssaidi@eecs.umich.edu    };
3325103Ssaidi@eecs.umich.edu
3339442SAndreas.Sandberg@ARM.com    /**
3349442SAndreas.Sandberg@ARM.com     * Check if a system is in a drained state.
3359442SAndreas.Sandberg@ARM.com     *
3369442SAndreas.Sandberg@ARM.com     * We need to drain if:
3379442SAndreas.Sandberg@ARM.com     * <ul>
3389442SAndreas.Sandberg@ARM.com     * <li>We are in the middle of a microcode sequence as some CPUs
3399442SAndreas.Sandberg@ARM.com     *     (e.g., HW accelerated CPUs) can't be started in the middle
3409442SAndreas.Sandberg@ARM.com     *     of a gem5 microcode sequence.
3419442SAndreas.Sandberg@ARM.com     *
3429442SAndreas.Sandberg@ARM.com     * <li>Stay at PC is true.
3439830Sandreas.hansson@arm.com     *
3449830Sandreas.hansson@arm.com     * <li>A fetch event is scheduled. Normally this would never be the
3459840Sandreas.hansson@arm.com     *     case with microPC() == 0, but right after a context is
3469840Sandreas.hansson@arm.com     *     activated it can happen.
3479442SAndreas.Sandberg@ARM.com     * </ul>
3489442SAndreas.Sandberg@ARM.com     */
3499442SAndreas.Sandberg@ARM.com    bool isDrained() {
35011147Smitch.hayenga@arm.com        SimpleExecContext& t_info = *threadInfo[curThread];
35111147Smitch.hayenga@arm.com        SimpleThread* thread = t_info.thread;
35211147Smitch.hayenga@arm.com
35311147Smitch.hayenga@arm.com        return thread->microPC() == 0 && !t_info.stayAtPC &&
35411147Smitch.hayenga@arm.com               !fetchEvent.scheduled();
3559442SAndreas.Sandberg@ARM.com    }
3569442SAndreas.Sandberg@ARM.com
3579442SAndreas.Sandberg@ARM.com    /**
3589442SAndreas.Sandberg@ARM.com     * Try to complete a drain request.
3599442SAndreas.Sandberg@ARM.com     *
3609442SAndreas.Sandberg@ARM.com     * @returns true if the CPU is drained, false otherwise.
3619442SAndreas.Sandberg@ARM.com     */
3629442SAndreas.Sandberg@ARM.com    bool tryCompleteDrain();
3632623SN/A};
3642623SN/A
3652623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
366