timing.hh revision 10407
12623SN/A/*
29608Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited
39442SAndreas.Sandberg@ARM.com * All rights reserved
49442SAndreas.Sandberg@ARM.com *
59442SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69442SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79442SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89442SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99442SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109442SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119442SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129442SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139442SAndreas.Sandberg@ARM.com *
142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
152623SN/A * All rights reserved.
162623SN/A *
172623SN/A * Redistribution and use in source and binary forms, with or without
182623SN/A * modification, are permitted provided that the following conditions are
192623SN/A * met: redistributions of source code must retain the above copyright
202623SN/A * notice, this list of conditions and the following disclaimer;
212623SN/A * redistributions in binary form must reproduce the above copyright
222623SN/A * notice, this list of conditions and the following disclaimer in the
232623SN/A * documentation and/or other materials provided with the distribution;
242623SN/A * neither the name of the copyright holders nor the names of its
252623SN/A * contributors may be used to endorse or promote products derived from
262623SN/A * this software without specific prior written permission.
272623SN/A *
282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
412623SN/A */
422623SN/A
432623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__
442623SN/A#define __CPU_SIMPLE_TIMING_HH__
452623SN/A
462623SN/A#include "cpu/simple/base.hh"
476973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh"
485529Snate@binkert.org#include "params/TimingSimpleCPU.hh"
495529Snate@binkert.org
502623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU
512623SN/A{
522623SN/A  public:
532623SN/A
545529Snate@binkert.org    TimingSimpleCPU(TimingSimpleCPUParams * params);
552623SN/A    virtual ~TimingSimpleCPU();
562623SN/A
572623SN/A    virtual void init();
582623SN/A
592623SN/A  private:
602623SN/A
615728Sgblack@eecs.umich.edu    /*
625728Sgblack@eecs.umich.edu     * If an access needs to be broken into fragments, currently at most two,
635728Sgblack@eecs.umich.edu     * the the following two classes are used as the sender state of the
645728Sgblack@eecs.umich.edu     * packets so the CPU can keep track of everything. In the main packet
655728Sgblack@eecs.umich.edu     * sender state, there's an array with a spot for each fragment. If a
665728Sgblack@eecs.umich.edu     * fragment has already been accepted by the CPU, aka isn't waiting for
675728Sgblack@eecs.umich.edu     * a retry, it's pointer is NULL. After each fragment has successfully
685728Sgblack@eecs.umich.edu     * been processed, the "outstanding" counter is decremented. Once the
695728Sgblack@eecs.umich.edu     * count is zero, the entire larger access is complete.
705728Sgblack@eecs.umich.edu     */
715728Sgblack@eecs.umich.edu    class SplitMainSenderState : public Packet::SenderState
725728Sgblack@eecs.umich.edu    {
735728Sgblack@eecs.umich.edu      public:
745728Sgblack@eecs.umich.edu        int outstanding;
755728Sgblack@eecs.umich.edu        PacketPtr fragments[2];
765728Sgblack@eecs.umich.edu
775728Sgblack@eecs.umich.edu        int
785728Sgblack@eecs.umich.edu        getPendingFragment()
795728Sgblack@eecs.umich.edu        {
805728Sgblack@eecs.umich.edu            if (fragments[0]) {
815728Sgblack@eecs.umich.edu                return 0;
825728Sgblack@eecs.umich.edu            } else if (fragments[1]) {
835728Sgblack@eecs.umich.edu                return 1;
845728Sgblack@eecs.umich.edu            } else {
855728Sgblack@eecs.umich.edu                return -1;
865728Sgblack@eecs.umich.edu            }
875728Sgblack@eecs.umich.edu        }
885728Sgblack@eecs.umich.edu    };
895728Sgblack@eecs.umich.edu
905728Sgblack@eecs.umich.edu    class SplitFragmentSenderState : public Packet::SenderState
915728Sgblack@eecs.umich.edu    {
925728Sgblack@eecs.umich.edu      public:
935728Sgblack@eecs.umich.edu        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
945728Sgblack@eecs.umich.edu            bigPkt(_bigPkt), index(_index)
955728Sgblack@eecs.umich.edu        {}
965728Sgblack@eecs.umich.edu        PacketPtr bigPkt;
975728Sgblack@eecs.umich.edu        int index;
985728Sgblack@eecs.umich.edu
995728Sgblack@eecs.umich.edu        void
1005728Sgblack@eecs.umich.edu        clearFromParent()
1015728Sgblack@eecs.umich.edu        {
1025728Sgblack@eecs.umich.edu            SplitMainSenderState * main_send_state =
1035728Sgblack@eecs.umich.edu                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
1045728Sgblack@eecs.umich.edu            main_send_state->fragments[index] = NULL;
1055728Sgblack@eecs.umich.edu        }
1065728Sgblack@eecs.umich.edu    };
1075728Sgblack@eecs.umich.edu
1085894Sgblack@eecs.umich.edu    class FetchTranslation : public BaseTLB::Translation
1095894Sgblack@eecs.umich.edu    {
1105894Sgblack@eecs.umich.edu      protected:
1115894Sgblack@eecs.umich.edu        TimingSimpleCPU *cpu;
1125894Sgblack@eecs.umich.edu
1135894Sgblack@eecs.umich.edu      public:
1146023Snate@binkert.org        FetchTranslation(TimingSimpleCPU *_cpu)
1156023Snate@binkert.org            : cpu(_cpu)
1165894Sgblack@eecs.umich.edu        {}
1175894Sgblack@eecs.umich.edu
1186023Snate@binkert.org        void
1197944SGiacomo.Gabrielli@arm.com        markDelayed()
1207945SAli.Saidi@ARM.com        {
1219342SAndreas.Sandberg@arm.com            assert(cpu->_status == BaseSimpleCPU::Running);
1227945SAli.Saidi@ARM.com            cpu->_status = ITBWaitResponse;
1237945SAli.Saidi@ARM.com        }
1247944SGiacomo.Gabrielli@arm.com
1257944SGiacomo.Gabrielli@arm.com        void
12610379Sandreas.hansson@arm.com        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
1276023Snate@binkert.org               BaseTLB::Mode mode)
1285894Sgblack@eecs.umich.edu        {
1295894Sgblack@eecs.umich.edu            cpu->sendFetch(fault, req, tc);
1305894Sgblack@eecs.umich.edu        }
1315894Sgblack@eecs.umich.edu    };
1325894Sgblack@eecs.umich.edu    FetchTranslation fetchTranslation;
1335894Sgblack@eecs.umich.edu
1346973Stjones1@inf.ed.ac.uk    void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
1356973Stjones1@inf.ed.ac.uk    void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
1366973Stjones1@inf.ed.ac.uk                       uint8_t *data, bool read);
1375894Sgblack@eecs.umich.edu
13810379Sandreas.hansson@arm.com    void translationFault(const Fault &fault);
1395894Sgblack@eecs.umich.edu
1405894Sgblack@eecs.umich.edu    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
1415894Sgblack@eecs.umich.edu    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
1425894Sgblack@eecs.umich.edu            RequestPtr req1, RequestPtr req2, RequestPtr req,
1435894Sgblack@eecs.umich.edu            uint8_t *data, bool read);
1445744Sgblack@eecs.umich.edu
1455728Sgblack@eecs.umich.edu    bool handleReadPacket(PacketPtr pkt);
1465728Sgblack@eecs.umich.edu    // This function always implicitly uses dcache_pkt.
1475728Sgblack@eecs.umich.edu    bool handleWritePacket();
1485728Sgblack@eecs.umich.edu
1498707Sandreas.hansson@arm.com    /**
1508707Sandreas.hansson@arm.com     * A TimingCPUPort overrides the default behaviour of the
1518707Sandreas.hansson@arm.com     * recvTiming and recvRetry and implements events for the
1528707Sandreas.hansson@arm.com     * scheduling of handling of incoming packets in the following
1538707Sandreas.hansson@arm.com     * cycle.
1548707Sandreas.hansson@arm.com     */
1559608Sandreas.hansson@arm.com    class TimingCPUPort : public MasterPort
1562623SN/A    {
1572623SN/A      public:
1582623SN/A
1598707Sandreas.hansson@arm.com        TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
1609608Sandreas.hansson@arm.com            : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this)
1612623SN/A        { }
1622623SN/A
1632623SN/A      protected:
1642623SN/A
1658948Sandreas.hansson@arm.com        /**
1668948Sandreas.hansson@arm.com         * Snooping a coherence request, do nothing.
1678948Sandreas.hansson@arm.com         */
16810030SAli.Saidi@ARM.com        virtual void recvTimingSnoopReq(PacketPtr pkt) {}
1698948Sandreas.hansson@arm.com
1708707Sandreas.hansson@arm.com        TimingSimpleCPU* cpu;
1712948Ssaidi@eecs.umich.edu
1722948Ssaidi@eecs.umich.edu        struct TickEvent : public Event
1732948Ssaidi@eecs.umich.edu        {
1743349Sbinkertn@umich.edu            PacketPtr pkt;
1752948Ssaidi@eecs.umich.edu            TimingSimpleCPU *cpu;
1762948Ssaidi@eecs.umich.edu
1778707Sandreas.hansson@arm.com            TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
1785336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU tick"; }
1793349Sbinkertn@umich.edu            void schedule(PacketPtr _pkt, Tick t);
1802948Ssaidi@eecs.umich.edu        };
1812948Ssaidi@eecs.umich.edu
1829087Sandreas.hansson@arm.com        EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent;
1832623SN/A    };
1842623SN/A
1858707Sandreas.hansson@arm.com    class IcachePort : public TimingCPUPort
1862623SN/A    {
1872623SN/A      public:
1882623SN/A
1898707Sandreas.hansson@arm.com        IcachePort(TimingSimpleCPU *_cpu)
1909095Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
1918707Sandreas.hansson@arm.com              tickEvent(_cpu)
1922623SN/A        { }
1932623SN/A
1942623SN/A      protected:
1952623SN/A
1968975Sandreas.hansson@arm.com        virtual bool recvTimingResp(PacketPtr pkt);
1972623SN/A
1982657Ssaidi@eecs.umich.edu        virtual void recvRetry();
1992948Ssaidi@eecs.umich.edu
2002948Ssaidi@eecs.umich.edu        struct ITickEvent : public TickEvent
2012948Ssaidi@eecs.umich.edu        {
2022948Ssaidi@eecs.umich.edu
2032948Ssaidi@eecs.umich.edu            ITickEvent(TimingSimpleCPU *_cpu)
2042948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2052948Ssaidi@eecs.umich.edu            void process();
2065336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU icache tick"; }
2072948Ssaidi@eecs.umich.edu        };
2082948Ssaidi@eecs.umich.edu
2092948Ssaidi@eecs.umich.edu        ITickEvent tickEvent;
2102948Ssaidi@eecs.umich.edu
2112623SN/A    };
2122623SN/A
2138707Sandreas.hansson@arm.com    class DcachePort : public TimingCPUPort
2142623SN/A    {
2152623SN/A      public:
2162623SN/A
2178707Sandreas.hansson@arm.com        DcachePort(TimingSimpleCPU *_cpu)
2189095Sandreas.hansson@arm.com            : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
2199095Sandreas.hansson@arm.com              tickEvent(_cpu)
22010030SAli.Saidi@ARM.com        {
22110030SAli.Saidi@ARM.com           cacheBlockMask = ~(cpu->cacheLineSize() - 1);
22210030SAli.Saidi@ARM.com        }
2232623SN/A
22410030SAli.Saidi@ARM.com        Addr cacheBlockMask;
2252623SN/A      protected:
2262623SN/A
22710030SAli.Saidi@ARM.com        /** Snoop a coherence request, we need to check if this causes
22810030SAli.Saidi@ARM.com         * a wakeup event on a cpu that is monitoring an address
22910030SAli.Saidi@ARM.com         */
23010030SAli.Saidi@ARM.com        virtual void recvTimingSnoopReq(PacketPtr pkt);
23110030SAli.Saidi@ARM.com
2328975Sandreas.hansson@arm.com        virtual bool recvTimingResp(PacketPtr pkt);
2332623SN/A
2342657Ssaidi@eecs.umich.edu        virtual void recvRetry();
2352948Ssaidi@eecs.umich.edu
2362948Ssaidi@eecs.umich.edu        struct DTickEvent : public TickEvent
2372948Ssaidi@eecs.umich.edu        {
2382948Ssaidi@eecs.umich.edu            DTickEvent(TimingSimpleCPU *_cpu)
2392948Ssaidi@eecs.umich.edu                : TickEvent(_cpu) {}
2402948Ssaidi@eecs.umich.edu            void process();
2415336Shines@cs.fsu.edu            const char *description() const { return "Timing CPU dcache tick"; }
2422948Ssaidi@eecs.umich.edu        };
2432948Ssaidi@eecs.umich.edu
2442948Ssaidi@eecs.umich.edu        DTickEvent tickEvent;
2452948Ssaidi@eecs.umich.edu
2462623SN/A    };
2472623SN/A
2482623SN/A    IcachePort icachePort;
2492623SN/A    DcachePort dcachePort;
2502623SN/A
2513349Sbinkertn@umich.edu    PacketPtr ifetch_pkt;
2523349Sbinkertn@umich.edu    PacketPtr dcache_pkt;
2532623SN/A
2549179Sandreas.hansson@arm.com    Tick previousCycle;
2553170Sstever@eecs.umich.edu
2568850Sandreas.hansson@arm.com  protected:
2578850Sandreas.hansson@arm.com
2588850Sandreas.hansson@arm.com     /** Return a reference to the data port. */
2599608Sandreas.hansson@arm.com    virtual MasterPort &getDataPort() { return dcachePort; }
2608850Sandreas.hansson@arm.com
2618850Sandreas.hansson@arm.com    /** Return a reference to the instruction port. */
2629608Sandreas.hansson@arm.com    virtual MasterPort &getInstPort() { return icachePort; }
2638850Sandreas.hansson@arm.com
2642623SN/A  public:
2652623SN/A
2669342SAndreas.Sandberg@arm.com    unsigned int drain(DrainManager *drain_manager);
2679342SAndreas.Sandberg@arm.com    void drainResume();
2682798Sktlim@umich.edu
2692798Sktlim@umich.edu    void switchOut();
2702623SN/A    void takeOverFrom(BaseCPU *oldCPU);
2712623SN/A
2729523SAndreas.Sandberg@ARM.com    void verifyMemoryMode() const;
2739523SAndreas.Sandberg@ARM.com
27410407Smitch.hayenga@arm.com    virtual void activateContext(ThreadID thread_num);
2758737Skoansin.tan@gmail.com    virtual void suspendContext(ThreadID thread_num);
2762623SN/A
2778444Sgblack@eecs.umich.edu    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
2787520Sgblack@eecs.umich.edu
2798444Sgblack@eecs.umich.edu    Fault writeMem(uint8_t *data, unsigned size,
2808444Sgblack@eecs.umich.edu                   Addr addr, unsigned flags, uint64_t *res);
2817520Sgblack@eecs.umich.edu
2822623SN/A    void fetch();
28310379Sandreas.hansson@arm.com    void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
2843349Sbinkertn@umich.edu    void completeIfetch(PacketPtr );
2855894Sgblack@eecs.umich.edu    void completeDataAccess(PacketPtr pkt);
28610379Sandreas.hansson@arm.com    void advanceInst(const Fault &fault);
2874471Sstever@eecs.umich.edu
2889258SAli.Saidi@ARM.com    /** This function is used by the page table walker to determine if it could
2899258SAli.Saidi@ARM.com     * translate the a pending request or if the underlying request has been
2909258SAli.Saidi@ARM.com     * squashed. This always returns false for the simple timing CPU as it never
2919258SAli.Saidi@ARM.com     * executes any instructions speculatively.
2929258SAli.Saidi@ARM.com     * @ return Is the current instruction squashed?
2939258SAli.Saidi@ARM.com     */
2949258SAli.Saidi@ARM.com    bool isSquashed() const { return false; }
2959258SAli.Saidi@ARM.com
2965315Sstever@gmail.com    /**
2975315Sstever@gmail.com     * Print state of address in memory system via PrintReq (for
2985315Sstever@gmail.com     * debugging).
2995315Sstever@gmail.com     */
3005315Sstever@gmail.com    void printAddr(Addr a);
3015315Sstever@gmail.com
3026973Stjones1@inf.ed.ac.uk    /**
3036973Stjones1@inf.ed.ac.uk     * Finish a DTB translation.
3046973Stjones1@inf.ed.ac.uk     * @param state The DTB translation state.
3056973Stjones1@inf.ed.ac.uk     */
3066973Stjones1@inf.ed.ac.uk    void finishTranslation(WholeTranslationState *state);
3076973Stjones1@inf.ed.ac.uk
3082798Sktlim@umich.edu  private:
3094471Sstever@eecs.umich.edu
3104471Sstever@eecs.umich.edu    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
3115710Scws3k@cs.virginia.edu    FetchEvent fetchEvent;
3124471Sstever@eecs.umich.edu
3135103Ssaidi@eecs.umich.edu    struct IprEvent : Event {
3145103Ssaidi@eecs.umich.edu        Packet *pkt;
3155103Ssaidi@eecs.umich.edu        TimingSimpleCPU *cpu;
3165103Ssaidi@eecs.umich.edu        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
3175103Ssaidi@eecs.umich.edu        virtual void process();
3185336Shines@cs.fsu.edu        virtual const char *description() const;
3195103Ssaidi@eecs.umich.edu    };
3205103Ssaidi@eecs.umich.edu
3219442SAndreas.Sandberg@ARM.com    /**
3229442SAndreas.Sandberg@ARM.com     * Check if a system is in a drained state.
3239442SAndreas.Sandberg@ARM.com     *
3249442SAndreas.Sandberg@ARM.com     * We need to drain if:
3259442SAndreas.Sandberg@ARM.com     * <ul>
3269442SAndreas.Sandberg@ARM.com     * <li>We are in the middle of a microcode sequence as some CPUs
3279442SAndreas.Sandberg@ARM.com     *     (e.g., HW accelerated CPUs) can't be started in the middle
3289442SAndreas.Sandberg@ARM.com     *     of a gem5 microcode sequence.
3299442SAndreas.Sandberg@ARM.com     *
3309442SAndreas.Sandberg@ARM.com     * <li>Stay at PC is true.
3319830Sandreas.hansson@arm.com     *
3329830Sandreas.hansson@arm.com     * <li>A fetch event is scheduled. Normally this would never be the
3339840Sandreas.hansson@arm.com     *     case with microPC() == 0, but right after a context is
3349840Sandreas.hansson@arm.com     *     activated it can happen.
3359442SAndreas.Sandberg@ARM.com     * </ul>
3369442SAndreas.Sandberg@ARM.com     */
3379442SAndreas.Sandberg@ARM.com    bool isDrained() {
3389830Sandreas.hansson@arm.com        return microPC() == 0 && !stayAtPC && !fetchEvent.scheduled();
3399442SAndreas.Sandberg@ARM.com    }
3409442SAndreas.Sandberg@ARM.com
3419442SAndreas.Sandberg@ARM.com    /**
3429442SAndreas.Sandberg@ARM.com     * Try to complete a drain request.
3439442SAndreas.Sandberg@ARM.com     *
3449442SAndreas.Sandberg@ARM.com     * @returns true if the CPU is drained, false otherwise.
3459442SAndreas.Sandberg@ARM.com     */
3469442SAndreas.Sandberg@ARM.com    bool tryCompleteDrain();
3479442SAndreas.Sandberg@ARM.com
3489442SAndreas.Sandberg@ARM.com    /**
3499442SAndreas.Sandberg@ARM.com     * Drain manager to use when signaling drain completion
3509442SAndreas.Sandberg@ARM.com     *
3519442SAndreas.Sandberg@ARM.com     * This pointer is non-NULL when draining and NULL otherwise.
3529442SAndreas.Sandberg@ARM.com     */
3539442SAndreas.Sandberg@ARM.com    DrainManager *drainManager;
3542623SN/A};
3552623SN/A
3562623SN/A#endif // __CPU_SIMPLE_TIMING_HH__
357