timing.cc revision 5712
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 655712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1035606Snate@binkert.org cpu->schedule(this, t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1065529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1075710Scws3k@cs.virginia.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1465496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1595221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1635710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1645710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1652915Sktlim@umich.edu 1665710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1672623SN/A } 1682798Sktlim@umich.edu 1692901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1702798Sktlim@umich.edu} 1712798Sktlim@umich.edu 1722798Sktlim@umich.eduvoid 1732798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1742798Sktlim@umich.edu{ 1755496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1762798Sktlim@umich.edu _status = SwitchedOut; 1775099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1782867Sktlim@umich.edu 1792867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1802867Sktlim@umich.edu // we'll need to cancel it. 1815710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1825606Snate@binkert.org deschedule(fetchEvent); 1832623SN/A} 1842623SN/A 1852623SN/A 1862623SN/Avoid 1872623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1882623SN/A{ 1894192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1902623SN/A 1912680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1922623SN/A // running and schedule its tick event. 1932680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1942680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1952680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1962623SN/A _status = Running; 1972623SN/A break; 1982623SN/A } 1992623SN/A } 2003201Shsul@eecs.umich.edu 2013201Shsul@eecs.umich.edu if (_status != Running) { 2023201Shsul@eecs.umich.edu _status = Idle; 2033201Shsul@eecs.umich.edu } 2045169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2055712Shsul@eecs.umich.edu _cpuId = tc->cpuId(); 2065101Ssaidi@eecs.umich.edu previousTick = curTick; 2072623SN/A} 2082623SN/A 2092623SN/A 2102623SN/Avoid 2112623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2122623SN/A{ 2135221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2145221Ssaidi@eecs.umich.edu 2152623SN/A assert(thread_num == 0); 2162683Sktlim@umich.edu assert(thread); 2172623SN/A 2182623SN/A assert(_status == Idle); 2192623SN/A 2202623SN/A notIdleFraction++; 2212623SN/A _status = Running; 2223686Sktlim@umich.edu 2232623SN/A // kick things off by initiating the fetch of the next instruction 2245606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2252623SN/A} 2262623SN/A 2272623SN/A 2282623SN/Avoid 2292623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2302623SN/A{ 2315221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2325221Ssaidi@eecs.umich.edu 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362644Sstever@eecs.umich.edu assert(_status == Running); 2372623SN/A 2382644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2392644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2402623SN/A 2412623SN/A notIdleFraction--; 2422623SN/A _status = Idle; 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Atemplate <class T> 2472623SN/AFault 2482623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2492623SN/A{ 2503169Sstever@eecs.umich.edu Request *req = 2513169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2525712Shsul@eecs.umich.edu _cpuId, /* thread ID */ 0); 2532623SN/A 2542623SN/A if (traceData) { 2553169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2562623SN/A } 2572623SN/A 2582623SN/A // translate to physical address 2593169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2602623SN/A 2612623SN/A // Now do the access. 2622623SN/A if (fault == NoFault) { 2633349Sbinkertn@umich.edu PacketPtr pkt = 2644878Sstever@eecs.umich.edu new Packet(req, 2654878Sstever@eecs.umich.edu (req->isLocked() ? 2664878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2674878Sstever@eecs.umich.edu Packet::Broadcast); 2683169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2692623SN/A 2705103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2715103Ssaidi@eecs.umich.edu Tick delay; 2725103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2735103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2745103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2755103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2765103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2772623SN/A _status = DcacheRetry; 2783169Sstever@eecs.umich.edu dcache_pkt = pkt; 2792623SN/A } else { 2802623SN/A _status = DcacheWaitResponse; 2813169Sstever@eecs.umich.edu // memory system takes ownership of packet 2822623SN/A dcache_pkt = NULL; 2832623SN/A } 2844200Ssaidi@eecs.umich.edu 2854200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2864200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2874200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2883658Sktlim@umich.edu } else { 2893658Sktlim@umich.edu delete req; 2902623SN/A } 2912623SN/A 2925408Sgblack@eecs.umich.edu if (traceData) { 2935408Sgblack@eecs.umich.edu traceData->setData(data); 2945408Sgblack@eecs.umich.edu } 2952623SN/A return fault; 2962623SN/A} 2972623SN/A 2985177Sgblack@eecs.umich.eduFault 2995177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3005177Sgblack@eecs.umich.edu int size, unsigned flags) 3015177Sgblack@eecs.umich.edu{ 3025177Sgblack@eecs.umich.edu Request *req = 3035712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 3045177Sgblack@eecs.umich.edu 3055177Sgblack@eecs.umich.edu if (traceData) { 3065177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3075177Sgblack@eecs.umich.edu } 3085177Sgblack@eecs.umich.edu 3095177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3105177Sgblack@eecs.umich.edu 3115177Sgblack@eecs.umich.edu if (fault == NoFault) 3125177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3135177Sgblack@eecs.umich.edu 3145177Sgblack@eecs.umich.edu delete req; 3155177Sgblack@eecs.umich.edu return fault; 3165177Sgblack@eecs.umich.edu} 3175177Sgblack@eecs.umich.edu 3182623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3192623SN/A 3202623SN/Atemplate 3212623SN/AFault 3224040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3234040Ssaidi@eecs.umich.edu 3244040Ssaidi@eecs.umich.edutemplate 3254040Ssaidi@eecs.umich.eduFault 3264115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3274115Ssaidi@eecs.umich.edu 3284115Ssaidi@eecs.umich.edutemplate 3294115Ssaidi@eecs.umich.eduFault 3302623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3312623SN/A 3322623SN/Atemplate 3332623SN/AFault 3342623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3352623SN/A 3362623SN/Atemplate 3372623SN/AFault 3382623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3392623SN/A 3402623SN/Atemplate 3412623SN/AFault 3422623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3432623SN/A 3442623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3452623SN/A 3462623SN/Atemplate<> 3472623SN/AFault 3482623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3492623SN/A{ 3502623SN/A return read(addr, *(uint64_t*)&data, flags); 3512623SN/A} 3522623SN/A 3532623SN/Atemplate<> 3542623SN/AFault 3552623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3562623SN/A{ 3572623SN/A return read(addr, *(uint32_t*)&data, flags); 3582623SN/A} 3592623SN/A 3602623SN/A 3612623SN/Atemplate<> 3622623SN/AFault 3632623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3642623SN/A{ 3652623SN/A return read(addr, (uint32_t&)data, flags); 3662623SN/A} 3672623SN/A 3682623SN/A 3692623SN/Atemplate <class T> 3702623SN/AFault 3712623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3722623SN/A{ 3733169Sstever@eecs.umich.edu Request *req = 3743169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3755712Shsul@eecs.umich.edu _cpuId, /* thread ID */ 0); 3762623SN/A 3774040Ssaidi@eecs.umich.edu if (traceData) { 3784040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3794040Ssaidi@eecs.umich.edu } 3804040Ssaidi@eecs.umich.edu 3812623SN/A // translate to physical address 3823169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3833169Sstever@eecs.umich.edu 3842623SN/A // Now do the access. 3852623SN/A if (fault == NoFault) { 3864878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3873170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3883170Sstever@eecs.umich.edu 3893170Sstever@eecs.umich.edu if (req->isLocked()) { 3904878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3913170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3924878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3934878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3944878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3954878Sstever@eecs.umich.edu assert(res); 3964878Sstever@eecs.umich.edu req->setExtraData(*res); 3974878Sstever@eecs.umich.edu } 3983170Sstever@eecs.umich.edu } 3994584Ssaidi@eecs.umich.edu 4004881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4014881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4024881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4034881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4044881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4054881Sstever@eecs.umich.edu dcache_pkt->set(data); 4063170Sstever@eecs.umich.edu 4073170Sstever@eecs.umich.edu if (do_access) { 4085103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4095103Ssaidi@eecs.umich.edu Tick delay; 4105103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4115103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4125103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4135103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4145103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4155103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4163170Sstever@eecs.umich.edu _status = DcacheRetry; 4173170Sstever@eecs.umich.edu } else { 4183170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4193170Sstever@eecs.umich.edu // memory system takes ownership of packet 4203170Sstever@eecs.umich.edu dcache_pkt = NULL; 4213170Sstever@eecs.umich.edu } 4222623SN/A } 4234200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4244200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4254200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4263658Sktlim@umich.edu } else { 4273658Sktlim@umich.edu delete req; 4282623SN/A } 4292623SN/A 4305408Sgblack@eecs.umich.edu if (traceData) { 4315408Sgblack@eecs.umich.edu traceData->setData(data); 4325408Sgblack@eecs.umich.edu } 4332623SN/A 4342623SN/A // If the write needs to have a fault on the access, consider calling 4352623SN/A // changeStatus() and changing it to "bad addr write" or something. 4362623SN/A return fault; 4372623SN/A} 4382623SN/A 4395177Sgblack@eecs.umich.eduFault 4405177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4415177Sgblack@eecs.umich.edu int size, unsigned flags) 4425177Sgblack@eecs.umich.edu{ 4435177Sgblack@eecs.umich.edu Request *req = 4445712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 4455177Sgblack@eecs.umich.edu 4465177Sgblack@eecs.umich.edu if (traceData) { 4475177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4485177Sgblack@eecs.umich.edu } 4495177Sgblack@eecs.umich.edu 4505177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4515177Sgblack@eecs.umich.edu 4525177Sgblack@eecs.umich.edu if (fault == NoFault) 4535177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4545177Sgblack@eecs.umich.edu 4555177Sgblack@eecs.umich.edu delete req; 4565177Sgblack@eecs.umich.edu return fault; 4575177Sgblack@eecs.umich.edu} 4585177Sgblack@eecs.umich.edu 4592623SN/A 4602623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4612623SN/Atemplate 4622623SN/AFault 4634224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4644224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4654224Sgblack@eecs.umich.edu 4664224Sgblack@eecs.umich.edutemplate 4674224Sgblack@eecs.umich.eduFault 4684224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4694224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4704224Sgblack@eecs.umich.edu 4714224Sgblack@eecs.umich.edutemplate 4724224Sgblack@eecs.umich.eduFault 4732623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4742623SN/A unsigned flags, uint64_t *res); 4752623SN/A 4762623SN/Atemplate 4772623SN/AFault 4782623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4792623SN/A unsigned flags, uint64_t *res); 4802623SN/A 4812623SN/Atemplate 4822623SN/AFault 4832623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4842623SN/A unsigned flags, uint64_t *res); 4852623SN/A 4862623SN/Atemplate 4872623SN/AFault 4882623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4892623SN/A unsigned flags, uint64_t *res); 4902623SN/A 4912623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4922623SN/A 4932623SN/Atemplate<> 4942623SN/AFault 4952623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4962623SN/A{ 4972623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4982623SN/A} 4992623SN/A 5002623SN/Atemplate<> 5012623SN/AFault 5022623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5032623SN/A{ 5042623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5052623SN/A} 5062623SN/A 5072623SN/A 5082623SN/Atemplate<> 5092623SN/AFault 5102623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5112623SN/A{ 5122623SN/A return write((uint32_t)data, addr, flags, res); 5132623SN/A} 5142623SN/A 5152623SN/A 5162623SN/Avoid 5172623SN/ATimingSimpleCPU::fetch() 5182623SN/A{ 5195221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5205221Ssaidi@eecs.umich.edu 5213387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5223387Sgblack@eecs.umich.edu checkForInterrupts(); 5232631SN/A 5245348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5255348Ssaidi@eecs.umich.edu 5265669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 5272623SN/A 5285669Sgblack@eecs.umich.edu if (!fromRom) { 5295669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5305712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5315669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5322623SN/A 5335669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5345669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5355669Sgblack@eecs.umich.edu 5365669Sgblack@eecs.umich.edu if (fault == NoFault) { 5375669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 5385669Sgblack@eecs.umich.edu // Need to wait for retry 5395669Sgblack@eecs.umich.edu _status = IcacheRetry; 5405669Sgblack@eecs.umich.edu } else { 5415669Sgblack@eecs.umich.edu // Need to wait for cache to respond 5425669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5435669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5445669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5455669Sgblack@eecs.umich.edu } 5462623SN/A } else { 5475669Sgblack@eecs.umich.edu delete ifetch_req; 5485669Sgblack@eecs.umich.edu delete ifetch_pkt; 5495669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5505669Sgblack@eecs.umich.edu advanceInst(fault); 5512623SN/A } 5522623SN/A } else { 5535669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5545669Sgblack@eecs.umich.edu completeIfetch(NULL); 5552623SN/A } 5563222Sktlim@umich.edu 5575099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5583222Sktlim@umich.edu previousTick = curTick; 5592623SN/A} 5602623SN/A 5612623SN/A 5622623SN/Avoid 5632644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5642623SN/A{ 5652623SN/A advancePC(fault); 5662623SN/A 5672631SN/A if (_status == Running) { 5682631SN/A // kick off fetch of next instruction... callback from icache 5692631SN/A // response will cause that instruction to be executed, 5702631SN/A // keeping the CPU running. 5712631SN/A fetch(); 5722631SN/A } 5732623SN/A} 5742623SN/A 5752623SN/A 5762623SN/Avoid 5773349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5782623SN/A{ 5795221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5805221Ssaidi@eecs.umich.edu 5812623SN/A // received a response from the icache: execute the received 5822623SN/A // instruction 5835669Sgblack@eecs.umich.edu 5845669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 5852623SN/A assert(_status == IcacheWaitResponse); 5862798Sktlim@umich.edu 5872623SN/A _status = Running; 5882644Sstever@eecs.umich.edu 5895099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5903222Sktlim@umich.edu previousTick = curTick; 5913222Sktlim@umich.edu 5922839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5935669Sgblack@eecs.umich.edu if (pkt) { 5945669Sgblack@eecs.umich.edu delete pkt->req; 5955669Sgblack@eecs.umich.edu delete pkt; 5965669Sgblack@eecs.umich.edu } 5973658Sktlim@umich.edu 5982839Sktlim@umich.edu completeDrain(); 5992798Sktlim@umich.edu return; 6002798Sktlim@umich.edu } 6012798Sktlim@umich.edu 6022623SN/A preExecute(); 6032644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 6042623SN/A // load or store: just send to dcache 6052623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6063170Sstever@eecs.umich.edu if (_status != Running) { 6073170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 6083170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 6093170Sstever@eecs.umich.edu assert(fault == NoFault); 6102644Sstever@eecs.umich.edu } else { 6113170Sstever@eecs.umich.edu if (fault == NoFault) { 6125335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 6135335Shines@cs.fsu.edu // squashed due to predication 6143170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6155335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 6165335Shines@cs.fsu.edu 6173170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6183170Sstever@eecs.umich.edu traceData); 6195335Shines@cs.fsu.edu if (dcache_pkt != NULL) 6205335Shines@cs.fsu.edu { 6215335Shines@cs.fsu.edu delete dcache_pkt->req; 6225335Shines@cs.fsu.edu delete dcache_pkt; 6235335Shines@cs.fsu.edu dcache_pkt = NULL; 6245335Shines@cs.fsu.edu } 6254998Sgblack@eecs.umich.edu 6264998Sgblack@eecs.umich.edu // keep an instruction count 6274998Sgblack@eecs.umich.edu if (fault == NoFault) 6284998Sgblack@eecs.umich.edu countInst(); 6295001Sgblack@eecs.umich.edu } else if (traceData) { 6305001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6315001Sgblack@eecs.umich.edu delete traceData; 6325001Sgblack@eecs.umich.edu traceData = NULL; 6333170Sstever@eecs.umich.edu } 6344998Sgblack@eecs.umich.edu 6352644Sstever@eecs.umich.edu postExecute(); 6365103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6375103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6385103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6395103Ssaidi@eecs.umich.edu instCnt++; 6402644Sstever@eecs.umich.edu advanceInst(fault); 6412644Sstever@eecs.umich.edu } 6422623SN/A } else { 6432623SN/A // non-memory instruction: execute completely now 6442623SN/A Fault fault = curStaticInst->execute(this, traceData); 6454998Sgblack@eecs.umich.edu 6464998Sgblack@eecs.umich.edu // keep an instruction count 6474998Sgblack@eecs.umich.edu if (fault == NoFault) 6484998Sgblack@eecs.umich.edu countInst(); 6495001Sgblack@eecs.umich.edu else if (traceData) { 6505001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6515001Sgblack@eecs.umich.edu delete traceData; 6525001Sgblack@eecs.umich.edu traceData = NULL; 6535001Sgblack@eecs.umich.edu } 6544998Sgblack@eecs.umich.edu 6552644Sstever@eecs.umich.edu postExecute(); 6565103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6575103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6585103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6595103Ssaidi@eecs.umich.edu instCnt++; 6602644Sstever@eecs.umich.edu advanceInst(fault); 6612623SN/A } 6623658Sktlim@umich.edu 6635669Sgblack@eecs.umich.edu if (pkt) { 6645669Sgblack@eecs.umich.edu delete pkt->req; 6655669Sgblack@eecs.umich.edu delete pkt; 6665669Sgblack@eecs.umich.edu } 6672623SN/A} 6682623SN/A 6692948Ssaidi@eecs.umich.eduvoid 6702948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6712948Ssaidi@eecs.umich.edu{ 6722948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6732948Ssaidi@eecs.umich.edu} 6742623SN/A 6752623SN/Abool 6763349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6772623SN/A{ 6784986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6793310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6804584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6812948Ssaidi@eecs.umich.edu 6823495Sktlim@umich.edu if (next_tick == curTick) 6833310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6843310Srdreslin@umich.edu else 6853495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6862948Ssaidi@eecs.umich.edu 6873310Srdreslin@umich.edu return true; 6883310Srdreslin@umich.edu } 6894870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6904433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6914433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6924433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6934433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6944433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6954433Ssaidi@eecs.umich.edu } 6963310Srdreslin@umich.edu } 6974433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6984433Ssaidi@eecs.umich.edu return true; 6992623SN/A} 7002623SN/A 7012657Ssaidi@eecs.umich.eduvoid 7022623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7032623SN/A{ 7042623SN/A // we shouldn't get a retry unless we have a packet that we're 7052623SN/A // waiting to transmit 7062623SN/A assert(cpu->ifetch_pkt != NULL); 7072623SN/A assert(cpu->_status == IcacheRetry); 7083349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7092657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7102657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7112657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7122657Ssaidi@eecs.umich.edu } 7132623SN/A} 7142623SN/A 7152623SN/Avoid 7163349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7172623SN/A{ 7182623SN/A // received a response from the dcache: complete the load or store 7192623SN/A // instruction 7204870Sstever@eecs.umich.edu assert(!pkt->isError()); 7212623SN/A assert(_status == DcacheWaitResponse); 7222623SN/A _status = Running; 7232623SN/A 7245099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7253222Sktlim@umich.edu previousTick = curTick; 7263184Srdreslin@umich.edu 7272623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7282623SN/A 7294998Sgblack@eecs.umich.edu // keep an instruction count 7304998Sgblack@eecs.umich.edu if (fault == NoFault) 7314998Sgblack@eecs.umich.edu countInst(); 7325001Sgblack@eecs.umich.edu else if (traceData) { 7335001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7345001Sgblack@eecs.umich.edu delete traceData; 7355001Sgblack@eecs.umich.edu traceData = NULL; 7365001Sgblack@eecs.umich.edu } 7374998Sgblack@eecs.umich.edu 7385507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7395507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7405507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 7413170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7423170Sstever@eecs.umich.edu } 7433170Sstever@eecs.umich.edu 7442644Sstever@eecs.umich.edu delete pkt->req; 7452644Sstever@eecs.umich.edu delete pkt; 7462644Sstever@eecs.umich.edu 7473184Srdreslin@umich.edu postExecute(); 7483227Sktlim@umich.edu 7493201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7503201Shsul@eecs.umich.edu advancePC(fault); 7513201Shsul@eecs.umich.edu completeDrain(); 7523201Shsul@eecs.umich.edu 7533201Shsul@eecs.umich.edu return; 7543201Shsul@eecs.umich.edu } 7553201Shsul@eecs.umich.edu 7562644Sstever@eecs.umich.edu advanceInst(fault); 7572623SN/A} 7582623SN/A 7592623SN/A 7602798Sktlim@umich.eduvoid 7612839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7622798Sktlim@umich.edu{ 7632839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7642901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7652839Sktlim@umich.edu drainEvent->process(); 7662798Sktlim@umich.edu} 7672623SN/A 7684192Sktlim@umich.eduvoid 7694192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7704192Sktlim@umich.edu{ 7714192Sktlim@umich.edu Port::setPeer(port); 7724192Sktlim@umich.edu 7734192Sktlim@umich.edu#if FULL_SYSTEM 7744192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7754192Sktlim@umich.edu // Ports) 7765497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 7774192Sktlim@umich.edu#endif 7784192Sktlim@umich.edu} 7794192Sktlim@umich.edu 7802623SN/Abool 7813349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7822623SN/A{ 7834986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7843310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7854584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7862948Ssaidi@eecs.umich.edu 7873495Sktlim@umich.edu if (next_tick == curTick) 7883310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7893310Srdreslin@umich.edu else 7903495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7912948Ssaidi@eecs.umich.edu 7923310Srdreslin@umich.edu return true; 7933310Srdreslin@umich.edu } 7944870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7954433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7964433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7974433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7984433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7994433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 8004433Ssaidi@eecs.umich.edu } 8013310Srdreslin@umich.edu } 8024433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8034433Ssaidi@eecs.umich.edu return true; 8042948Ssaidi@eecs.umich.edu} 8052948Ssaidi@eecs.umich.edu 8062948Ssaidi@eecs.umich.eduvoid 8072948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8082948Ssaidi@eecs.umich.edu{ 8092630SN/A cpu->completeDataAccess(pkt); 8102623SN/A} 8112623SN/A 8122657Ssaidi@eecs.umich.eduvoid 8132623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8142623SN/A{ 8152623SN/A // we shouldn't get a retry unless we have a packet that we're 8162623SN/A // waiting to transmit 8172623SN/A assert(cpu->dcache_pkt != NULL); 8182623SN/A assert(cpu->_status == DcacheRetry); 8193349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8202657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8212657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8223170Sstever@eecs.umich.edu // memory system takes ownership of packet 8232657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8242657Ssaidi@eecs.umich.edu } 8252623SN/A} 8262623SN/A 8275606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8285606Snate@binkert.org Tick t) 8295606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8305103Ssaidi@eecs.umich.edu{ 8315606Snate@binkert.org cpu->schedule(this, t); 8325103Ssaidi@eecs.umich.edu} 8335103Ssaidi@eecs.umich.edu 8345103Ssaidi@eecs.umich.eduvoid 8355103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8365103Ssaidi@eecs.umich.edu{ 8375103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8385103Ssaidi@eecs.umich.edu} 8395103Ssaidi@eecs.umich.edu 8405103Ssaidi@eecs.umich.educonst char * 8415336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8425103Ssaidi@eecs.umich.edu{ 8435103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8445103Ssaidi@eecs.umich.edu} 8455103Ssaidi@eecs.umich.edu 8462623SN/A 8475315Sstever@gmail.comvoid 8485315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 8495315Sstever@gmail.com{ 8505315Sstever@gmail.com dcachePort.printAddr(a); 8515315Sstever@gmail.com} 8525315Sstever@gmail.com 8535315Sstever@gmail.com 8542623SN/A//////////////////////////////////////////////////////////////////////// 8552623SN/A// 8562623SN/A// TimingSimpleCPU Simulation Object 8572623SN/A// 8584762Snate@binkert.orgTimingSimpleCPU * 8594762Snate@binkert.orgTimingSimpleCPUParams::create() 8602623SN/A{ 8615529Snate@binkert.org numThreads = 1; 8625529Snate@binkert.org#if !FULL_SYSTEM 8634762Snate@binkert.org if (workload.size() != 1) 8644762Snate@binkert.org panic("only one workload allowed"); 8652623SN/A#endif 8665529Snate@binkert.org return new TimingSimpleCPU(this); 8672623SN/A} 868