timing.cc revision 5177
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 652680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1032948Ssaidi@eecs.umich.edu Event::schedule(t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1062623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1075169Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Delete the old event if it existed. 1642867Sktlim@umich.edu if (fetchEvent) { 1652915Sktlim@umich.edu if (fetchEvent->scheduled()) 1662915Sktlim@umich.edu fetchEvent->deschedule(); 1672915Sktlim@umich.edu 1682867Sktlim@umich.edu delete fetchEvent; 1692867Sktlim@umich.edu } 1702867Sktlim@umich.edu 1714471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1722623SN/A } 1732798Sktlim@umich.edu 1742901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1752798Sktlim@umich.edu} 1762798Sktlim@umich.edu 1772798Sktlim@umich.eduvoid 1782798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1792798Sktlim@umich.edu{ 1802798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1812798Sktlim@umich.edu _status = SwitchedOut; 1825099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1832867Sktlim@umich.edu 1842867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1852867Sktlim@umich.edu // we'll need to cancel it. 1862867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1872867Sktlim@umich.edu fetchEvent->deschedule(); 1882623SN/A} 1892623SN/A 1902623SN/A 1912623SN/Avoid 1922623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1944192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1952623SN/A 1962680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1972623SN/A // running and schedule its tick event. 1982680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1992680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2002680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2012623SN/A _status = Running; 2022623SN/A break; 2032623SN/A } 2042623SN/A } 2053201Shsul@eecs.umich.edu 2063201Shsul@eecs.umich.edu if (_status != Running) { 2073201Shsul@eecs.umich.edu _status = Idle; 2083201Shsul@eecs.umich.edu } 2095169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2105169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2115101Ssaidi@eecs.umich.edu previousTick = curTick; 2122623SN/A} 2132623SN/A 2142623SN/A 2152623SN/Avoid 2162623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2172623SN/A{ 2182623SN/A assert(thread_num == 0); 2192683Sktlim@umich.edu assert(thread); 2202623SN/A 2212623SN/A assert(_status == Idle); 2222623SN/A 2232623SN/A notIdleFraction++; 2242623SN/A _status = Running; 2253686Sktlim@umich.edu 2262623SN/A // kick things off by initiating the fetch of the next instruction 2275100Ssaidi@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 2282623SN/A} 2292623SN/A 2302623SN/A 2312623SN/Avoid 2322623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2332623SN/A{ 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2372644Sstever@eecs.umich.edu assert(_status == Running); 2382623SN/A 2392644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2402644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2412623SN/A 2422623SN/A notIdleFraction--; 2432623SN/A _status = Idle; 2442623SN/A} 2452623SN/A 2462623SN/A 2472623SN/Atemplate <class T> 2482623SN/AFault 2492623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2502623SN/A{ 2513169Sstever@eecs.umich.edu Request *req = 2523169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2535169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2542623SN/A 2552623SN/A if (traceData) { 2563169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2572623SN/A } 2582623SN/A 2592623SN/A // translate to physical address 2603169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2612623SN/A 2622623SN/A // Now do the access. 2632623SN/A if (fault == NoFault) { 2643349Sbinkertn@umich.edu PacketPtr pkt = 2654878Sstever@eecs.umich.edu new Packet(req, 2664878Sstever@eecs.umich.edu (req->isLocked() ? 2674878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2684878Sstever@eecs.umich.edu Packet::Broadcast); 2693169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2702623SN/A 2715103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2725103Ssaidi@eecs.umich.edu Tick delay; 2735103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2745103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2755103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2765103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2775103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2782623SN/A _status = DcacheRetry; 2793169Sstever@eecs.umich.edu dcache_pkt = pkt; 2802623SN/A } else { 2812623SN/A _status = DcacheWaitResponse; 2823169Sstever@eecs.umich.edu // memory system takes ownership of packet 2832623SN/A dcache_pkt = NULL; 2842623SN/A } 2854200Ssaidi@eecs.umich.edu 2864200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2874200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2884200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2893658Sktlim@umich.edu } else { 2903658Sktlim@umich.edu delete req; 2912623SN/A } 2922623SN/A 2932623SN/A return fault; 2942623SN/A} 2952623SN/A 2965177Sgblack@eecs.umich.eduFault 2975177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 2985177Sgblack@eecs.umich.edu int size, unsigned flags) 2995177Sgblack@eecs.umich.edu{ 3005177Sgblack@eecs.umich.edu Request *req = 3015177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3025177Sgblack@eecs.umich.edu 3035177Sgblack@eecs.umich.edu if (traceData) { 3045177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3055177Sgblack@eecs.umich.edu } 3065177Sgblack@eecs.umich.edu 3075177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3085177Sgblack@eecs.umich.edu 3095177Sgblack@eecs.umich.edu if (fault == NoFault) 3105177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3115177Sgblack@eecs.umich.edu 3125177Sgblack@eecs.umich.edu delete req; 3135177Sgblack@eecs.umich.edu return fault; 3145177Sgblack@eecs.umich.edu} 3155177Sgblack@eecs.umich.edu 3162623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3172623SN/A 3182623SN/Atemplate 3192623SN/AFault 3204040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3214040Ssaidi@eecs.umich.edu 3224040Ssaidi@eecs.umich.edutemplate 3234040Ssaidi@eecs.umich.eduFault 3244115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3254115Ssaidi@eecs.umich.edu 3264115Ssaidi@eecs.umich.edutemplate 3274115Ssaidi@eecs.umich.eduFault 3282623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3292623SN/A 3302623SN/Atemplate 3312623SN/AFault 3322623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3332623SN/A 3342623SN/Atemplate 3352623SN/AFault 3362623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3372623SN/A 3382623SN/Atemplate 3392623SN/AFault 3402623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3412623SN/A 3422623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3432623SN/A 3442623SN/Atemplate<> 3452623SN/AFault 3462623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3472623SN/A{ 3482623SN/A return read(addr, *(uint64_t*)&data, flags); 3492623SN/A} 3502623SN/A 3512623SN/Atemplate<> 3522623SN/AFault 3532623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3542623SN/A{ 3552623SN/A return read(addr, *(uint32_t*)&data, flags); 3562623SN/A} 3572623SN/A 3582623SN/A 3592623SN/Atemplate<> 3602623SN/AFault 3612623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3622623SN/A{ 3632623SN/A return read(addr, (uint32_t&)data, flags); 3642623SN/A} 3652623SN/A 3662623SN/A 3672623SN/Atemplate <class T> 3682623SN/AFault 3692623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3702623SN/A{ 3713169Sstever@eecs.umich.edu Request *req = 3723169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3735169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3742623SN/A 3754040Ssaidi@eecs.umich.edu if (traceData) { 3764040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3774040Ssaidi@eecs.umich.edu } 3784040Ssaidi@eecs.umich.edu 3792623SN/A // translate to physical address 3803169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3813169Sstever@eecs.umich.edu 3822623SN/A // Now do the access. 3832623SN/A if (fault == NoFault) { 3844878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3853170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3863170Sstever@eecs.umich.edu 3873170Sstever@eecs.umich.edu if (req->isLocked()) { 3884878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3893170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3904878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3914878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3924878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3934878Sstever@eecs.umich.edu assert(res); 3944878Sstever@eecs.umich.edu req->setExtraData(*res); 3954878Sstever@eecs.umich.edu } 3963170Sstever@eecs.umich.edu } 3974584Ssaidi@eecs.umich.edu 3984881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 3994881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4004881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4014881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4024881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4034881Sstever@eecs.umich.edu dcache_pkt->set(data); 4043170Sstever@eecs.umich.edu 4053170Sstever@eecs.umich.edu if (do_access) { 4065103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4075103Ssaidi@eecs.umich.edu Tick delay; 4085103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4095103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4105103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4115103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4125103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4135103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4143170Sstever@eecs.umich.edu _status = DcacheRetry; 4153170Sstever@eecs.umich.edu } else { 4163170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4173170Sstever@eecs.umich.edu // memory system takes ownership of packet 4183170Sstever@eecs.umich.edu dcache_pkt = NULL; 4193170Sstever@eecs.umich.edu } 4202623SN/A } 4214200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4224200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4234200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4243658Sktlim@umich.edu } else { 4253658Sktlim@umich.edu delete req; 4262623SN/A } 4272623SN/A 4282623SN/A 4292623SN/A // If the write needs to have a fault on the access, consider calling 4302623SN/A // changeStatus() and changing it to "bad addr write" or something. 4312623SN/A return fault; 4322623SN/A} 4332623SN/A 4345177Sgblack@eecs.umich.eduFault 4355177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4365177Sgblack@eecs.umich.edu int size, unsigned flags) 4375177Sgblack@eecs.umich.edu{ 4385177Sgblack@eecs.umich.edu Request *req = 4395177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4405177Sgblack@eecs.umich.edu 4415177Sgblack@eecs.umich.edu if (traceData) { 4425177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4435177Sgblack@eecs.umich.edu } 4445177Sgblack@eecs.umich.edu 4455177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4465177Sgblack@eecs.umich.edu 4475177Sgblack@eecs.umich.edu if (fault == NoFault) 4485177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4495177Sgblack@eecs.umich.edu 4505177Sgblack@eecs.umich.edu delete req; 4515177Sgblack@eecs.umich.edu return fault; 4525177Sgblack@eecs.umich.edu} 4535177Sgblack@eecs.umich.edu 4542623SN/A 4552623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4562623SN/Atemplate 4572623SN/AFault 4584224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4594224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4604224Sgblack@eecs.umich.edu 4614224Sgblack@eecs.umich.edutemplate 4624224Sgblack@eecs.umich.eduFault 4634224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4644224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4654224Sgblack@eecs.umich.edu 4664224Sgblack@eecs.umich.edutemplate 4674224Sgblack@eecs.umich.eduFault 4682623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4692623SN/A unsigned flags, uint64_t *res); 4702623SN/A 4712623SN/Atemplate 4722623SN/AFault 4732623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4742623SN/A unsigned flags, uint64_t *res); 4752623SN/A 4762623SN/Atemplate 4772623SN/AFault 4782623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4792623SN/A unsigned flags, uint64_t *res); 4802623SN/A 4812623SN/Atemplate 4822623SN/AFault 4832623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4842623SN/A unsigned flags, uint64_t *res); 4852623SN/A 4862623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4872623SN/A 4882623SN/Atemplate<> 4892623SN/AFault 4902623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4912623SN/A{ 4922623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4932623SN/A} 4942623SN/A 4952623SN/Atemplate<> 4962623SN/AFault 4972623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4982623SN/A{ 4992623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5002623SN/A} 5012623SN/A 5022623SN/A 5032623SN/Atemplate<> 5042623SN/AFault 5052623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5062623SN/A{ 5072623SN/A return write((uint32_t)data, addr, flags, res); 5082623SN/A} 5092623SN/A 5102623SN/A 5112623SN/Avoid 5122623SN/ATimingSimpleCPU::fetch() 5132623SN/A{ 5143387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5153387Sgblack@eecs.umich.edu checkForInterrupts(); 5162631SN/A 5172663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 5185169Ssaidi@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5192662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5202623SN/A 5214022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5222623SN/A ifetch_pkt->dataStatic(&inst); 5232623SN/A 5242623SN/A if (fault == NoFault) { 5252630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 5262623SN/A // Need to wait for retry 5272623SN/A _status = IcacheRetry; 5282623SN/A } else { 5292623SN/A // Need to wait for cache to respond 5302623SN/A _status = IcacheWaitResponse; 5312623SN/A // ownership of packet transferred to memory system 5322623SN/A ifetch_pkt = NULL; 5332623SN/A } 5342623SN/A } else { 5353658Sktlim@umich.edu delete ifetch_req; 5363658Sktlim@umich.edu delete ifetch_pkt; 5372644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5382644Sstever@eecs.umich.edu advanceInst(fault); 5392623SN/A } 5403222Sktlim@umich.edu 5415099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5423222Sktlim@umich.edu previousTick = curTick; 5432623SN/A} 5442623SN/A 5452623SN/A 5462623SN/Avoid 5472644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5482623SN/A{ 5492623SN/A advancePC(fault); 5502623SN/A 5512631SN/A if (_status == Running) { 5522631SN/A // kick off fetch of next instruction... callback from icache 5532631SN/A // response will cause that instruction to be executed, 5542631SN/A // keeping the CPU running. 5552631SN/A fetch(); 5562631SN/A } 5572623SN/A} 5582623SN/A 5592623SN/A 5602623SN/Avoid 5613349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5622623SN/A{ 5632623SN/A // received a response from the icache: execute the received 5642623SN/A // instruction 5654870Sstever@eecs.umich.edu assert(!pkt->isError()); 5662623SN/A assert(_status == IcacheWaitResponse); 5672798Sktlim@umich.edu 5682623SN/A _status = Running; 5692644Sstever@eecs.umich.edu 5705099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5713222Sktlim@umich.edu previousTick = curTick; 5723222Sktlim@umich.edu 5732839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5743658Sktlim@umich.edu delete pkt->req; 5753658Sktlim@umich.edu delete pkt; 5763658Sktlim@umich.edu 5772839Sktlim@umich.edu completeDrain(); 5782798Sktlim@umich.edu return; 5792798Sktlim@umich.edu } 5802798Sktlim@umich.edu 5812623SN/A preExecute(); 5822644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5832623SN/A // load or store: just send to dcache 5842623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5853170Sstever@eecs.umich.edu if (_status != Running) { 5863170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5873170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5883170Sstever@eecs.umich.edu assert(fault == NoFault); 5892644Sstever@eecs.umich.edu } else { 5903170Sstever@eecs.umich.edu if (fault == NoFault) { 5913170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5923170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5933170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5943170Sstever@eecs.umich.edu traceData); 5953170Sstever@eecs.umich.edu delete dcache_pkt->req; 5963170Sstever@eecs.umich.edu delete dcache_pkt; 5973170Sstever@eecs.umich.edu dcache_pkt = NULL; 5984998Sgblack@eecs.umich.edu 5994998Sgblack@eecs.umich.edu // keep an instruction count 6004998Sgblack@eecs.umich.edu if (fault == NoFault) 6014998Sgblack@eecs.umich.edu countInst(); 6025001Sgblack@eecs.umich.edu } else if (traceData) { 6035001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6045001Sgblack@eecs.umich.edu delete traceData; 6055001Sgblack@eecs.umich.edu traceData = NULL; 6063170Sstever@eecs.umich.edu } 6074998Sgblack@eecs.umich.edu 6082644Sstever@eecs.umich.edu postExecute(); 6095103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6105103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6115103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6125103Ssaidi@eecs.umich.edu instCnt++; 6132644Sstever@eecs.umich.edu advanceInst(fault); 6142644Sstever@eecs.umich.edu } 6152623SN/A } else { 6162623SN/A // non-memory instruction: execute completely now 6172623SN/A Fault fault = curStaticInst->execute(this, traceData); 6184998Sgblack@eecs.umich.edu 6194998Sgblack@eecs.umich.edu // keep an instruction count 6204998Sgblack@eecs.umich.edu if (fault == NoFault) 6214998Sgblack@eecs.umich.edu countInst(); 6225001Sgblack@eecs.umich.edu else if (traceData) { 6235001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6245001Sgblack@eecs.umich.edu delete traceData; 6255001Sgblack@eecs.umich.edu traceData = NULL; 6265001Sgblack@eecs.umich.edu } 6274998Sgblack@eecs.umich.edu 6282644Sstever@eecs.umich.edu postExecute(); 6295103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6305103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6315103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6325103Ssaidi@eecs.umich.edu instCnt++; 6332644Sstever@eecs.umich.edu advanceInst(fault); 6342623SN/A } 6353658Sktlim@umich.edu 6363658Sktlim@umich.edu delete pkt->req; 6373658Sktlim@umich.edu delete pkt; 6382623SN/A} 6392623SN/A 6402948Ssaidi@eecs.umich.eduvoid 6412948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6422948Ssaidi@eecs.umich.edu{ 6432948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6442948Ssaidi@eecs.umich.edu} 6452623SN/A 6462623SN/Abool 6473349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6482623SN/A{ 6494986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6503310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6514584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6522948Ssaidi@eecs.umich.edu 6533495Sktlim@umich.edu if (next_tick == curTick) 6543310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6553310Srdreslin@umich.edu else 6563495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6572948Ssaidi@eecs.umich.edu 6583310Srdreslin@umich.edu return true; 6593310Srdreslin@umich.edu } 6604870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6614433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6624433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6634433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6644433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6654433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6664433Ssaidi@eecs.umich.edu } 6673310Srdreslin@umich.edu } 6684433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6694433Ssaidi@eecs.umich.edu return true; 6702623SN/A} 6712623SN/A 6722657Ssaidi@eecs.umich.eduvoid 6732623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6742623SN/A{ 6752623SN/A // we shouldn't get a retry unless we have a packet that we're 6762623SN/A // waiting to transmit 6772623SN/A assert(cpu->ifetch_pkt != NULL); 6782623SN/A assert(cpu->_status == IcacheRetry); 6793349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6802657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6812657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 6822657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6832657Ssaidi@eecs.umich.edu } 6842623SN/A} 6852623SN/A 6862623SN/Avoid 6873349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6882623SN/A{ 6892623SN/A // received a response from the dcache: complete the load or store 6902623SN/A // instruction 6914870Sstever@eecs.umich.edu assert(!pkt->isError()); 6922623SN/A assert(_status == DcacheWaitResponse); 6932623SN/A _status = Running; 6942623SN/A 6955099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6963222Sktlim@umich.edu previousTick = curTick; 6973184Srdreslin@umich.edu 6982623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6992623SN/A 7004998Sgblack@eecs.umich.edu // keep an instruction count 7014998Sgblack@eecs.umich.edu if (fault == NoFault) 7024998Sgblack@eecs.umich.edu countInst(); 7035001Sgblack@eecs.umich.edu else if (traceData) { 7045001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7055001Sgblack@eecs.umich.edu delete traceData; 7065001Sgblack@eecs.umich.edu traceData = NULL; 7075001Sgblack@eecs.umich.edu } 7084998Sgblack@eecs.umich.edu 7094878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 7103170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7113170Sstever@eecs.umich.edu } 7123170Sstever@eecs.umich.edu 7132644Sstever@eecs.umich.edu delete pkt->req; 7142644Sstever@eecs.umich.edu delete pkt; 7152644Sstever@eecs.umich.edu 7163184Srdreslin@umich.edu postExecute(); 7173227Sktlim@umich.edu 7183201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7193201Shsul@eecs.umich.edu advancePC(fault); 7203201Shsul@eecs.umich.edu completeDrain(); 7213201Shsul@eecs.umich.edu 7223201Shsul@eecs.umich.edu return; 7233201Shsul@eecs.umich.edu } 7243201Shsul@eecs.umich.edu 7252644Sstever@eecs.umich.edu advanceInst(fault); 7262623SN/A} 7272623SN/A 7282623SN/A 7292798Sktlim@umich.eduvoid 7302839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7312798Sktlim@umich.edu{ 7322839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7332901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7342839Sktlim@umich.edu drainEvent->process(); 7352798Sktlim@umich.edu} 7362623SN/A 7374192Sktlim@umich.eduvoid 7384192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7394192Sktlim@umich.edu{ 7404192Sktlim@umich.edu Port::setPeer(port); 7414192Sktlim@umich.edu 7424192Sktlim@umich.edu#if FULL_SYSTEM 7434192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7444192Sktlim@umich.edu // Ports) 7454192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 7464192Sktlim@umich.edu#endif 7474192Sktlim@umich.edu} 7484192Sktlim@umich.edu 7492623SN/Abool 7503349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7512623SN/A{ 7524986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7533310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7544584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7552948Ssaidi@eecs.umich.edu 7563495Sktlim@umich.edu if (next_tick == curTick) 7573310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7583310Srdreslin@umich.edu else 7593495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7602948Ssaidi@eecs.umich.edu 7613310Srdreslin@umich.edu return true; 7623310Srdreslin@umich.edu } 7634870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7644433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7654433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7664433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7674433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7684433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7694433Ssaidi@eecs.umich.edu } 7703310Srdreslin@umich.edu } 7714433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7724433Ssaidi@eecs.umich.edu return true; 7732948Ssaidi@eecs.umich.edu} 7742948Ssaidi@eecs.umich.edu 7752948Ssaidi@eecs.umich.eduvoid 7762948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 7772948Ssaidi@eecs.umich.edu{ 7782630SN/A cpu->completeDataAccess(pkt); 7792623SN/A} 7802623SN/A 7812657Ssaidi@eecs.umich.eduvoid 7822623SN/ATimingSimpleCPU::DcachePort::recvRetry() 7832623SN/A{ 7842623SN/A // we shouldn't get a retry unless we have a packet that we're 7852623SN/A // waiting to transmit 7862623SN/A assert(cpu->dcache_pkt != NULL); 7872623SN/A assert(cpu->_status == DcacheRetry); 7883349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 7892657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7902657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 7913170Sstever@eecs.umich.edu // memory system takes ownership of packet 7922657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 7932657Ssaidi@eecs.umich.edu } 7942623SN/A} 7952623SN/A 7965103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) 7975103Ssaidi@eecs.umich.edu : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) 7985103Ssaidi@eecs.umich.edu{ 7995103Ssaidi@eecs.umich.edu schedule(t); 8005103Ssaidi@eecs.umich.edu} 8015103Ssaidi@eecs.umich.edu 8025103Ssaidi@eecs.umich.eduvoid 8035103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8045103Ssaidi@eecs.umich.edu{ 8055103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8065103Ssaidi@eecs.umich.edu} 8075103Ssaidi@eecs.umich.edu 8085103Ssaidi@eecs.umich.educonst char * 8095103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::description() 8105103Ssaidi@eecs.umich.edu{ 8115103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8125103Ssaidi@eecs.umich.edu} 8135103Ssaidi@eecs.umich.edu 8142623SN/A 8152623SN/A//////////////////////////////////////////////////////////////////////// 8162623SN/A// 8172623SN/A// TimingSimpleCPU Simulation Object 8182623SN/A// 8194762Snate@binkert.orgTimingSimpleCPU * 8204762Snate@binkert.orgTimingSimpleCPUParams::create() 8212623SN/A{ 8222623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 8234762Snate@binkert.org params->name = name; 8242623SN/A params->numberOfThreads = 1; 8252623SN/A params->max_insts_any_thread = max_insts_any_thread; 8262623SN/A params->max_insts_all_threads = max_insts_all_threads; 8272623SN/A params->max_loads_any_thread = max_loads_any_thread; 8282623SN/A params->max_loads_all_threads = max_loads_all_threads; 8293119Sktlim@umich.edu params->progress_interval = progress_interval; 8302623SN/A params->deferRegistration = defer_registration; 8312623SN/A params->clock = clock; 8323661Srdreslin@umich.edu params->phase = phase; 8332623SN/A params->functionTrace = function_trace; 8342623SN/A params->functionTraceStart = function_trace_start; 8352901Ssaidi@eecs.umich.edu params->system = system; 8363170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 8374776Sgblack@eecs.umich.edu params->tracer = tracer; 8382623SN/A 8392623SN/A params->itb = itb; 8402623SN/A params->dtb = dtb; 8414997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8422623SN/A params->profile = profile; 8433617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 8443617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 8453617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 8462623SN/A#else 8474762Snate@binkert.org if (workload.size() != 1) 8484762Snate@binkert.org panic("only one workload allowed"); 8494762Snate@binkert.org params->process = workload[0]; 8502623SN/A#endif 8512623SN/A 8522623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 8532623SN/A return cpu; 8542623SN/A} 855