base.hh revision 4998
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 411354SN/A#include "cpu/pc_event.hh" 421354SN/A#include "cpu/static_inst.hh" 432387SN/A#include "mem/packet.hh" 442387SN/A#include "mem/port.hh" 452387SN/A#include "mem/request.hh" 4656SN/A#include "sim/eventq.hh" 472SN/A 482SN/A// forward declarations 491858SN/A#if FULL_SYSTEM 502SN/Aclass Processor; 513453Sgblack@eecs.umich.edunamespace TheISA 523453Sgblack@eecs.umich.edu{ 533453Sgblack@eecs.umich.edu class ITB; 543453Sgblack@eecs.umich.edu class DTB; 553453Sgblack@eecs.umich.edu} 562462SN/Aclass MemObject; 572SN/A 58715SN/A#else 59715SN/A 60715SN/Aclass Process; 61715SN/A 622SN/A#endif // FULL_SYSTEM 632SN/A 643960Sgblack@eecs.umich.educlass RemoteGDB; 653960Sgblack@eecs.umich.educlass GDBListener; 663960Sgblack@eecs.umich.edu 674182Sgblack@eecs.umich.edunamespace TheISA 684182Sgblack@eecs.umich.edu{ 694182Sgblack@eecs.umich.edu class Predecoder; 704182Sgblack@eecs.umich.edu} 712680Sktlim@umich.educlass ThreadContext; 72237SN/Aclass Checkpoint; 732SN/A 742SN/Anamespace Trace { 752SN/A class InstRecord; 762SN/A} 772SN/A 782420SN/A 792623SN/Aclass BaseSimpleCPU : public BaseCPU 802SN/A{ 812107SN/A protected: 822159SN/A typedef TheISA::MiscReg MiscReg; 832455SN/A typedef TheISA::FloatReg FloatReg; 842455SN/A typedef TheISA::FloatRegBits FloatRegBits; 852386SN/A 862623SN/A protected: 872SN/A Trace::InstRecord *traceData; 881371SN/A 892SN/A public: 902SN/A void post_interrupt(int int_num, int index); 912SN/A 922SN/A void zero_fill_64(Addr addr) { 932SN/A static int warned = 0; 942SN/A if (!warned) { 952SN/A warn ("WH64 is not implemented"); 962SN/A warned = 1; 972SN/A } 982SN/A }; 992SN/A 1001400SN/A public: 1011400SN/A struct Params : public BaseCPU::Params 1021400SN/A { 1033453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1043453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1054997Sgblack@eecs.umich.edu#if !FULL_SYSTEM 1061400SN/A Process *process; 1072SN/A#endif 1081400SN/A }; 1092623SN/A BaseSimpleCPU(Params *params); 1102623SN/A virtual ~BaseSimpleCPU(); 1112SN/A 1121400SN/A public: 1132683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1142683Sktlim@umich.edu SimpleThread *thread; 1152190SN/A 1162683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1172683Sktlim@umich.edu * objects to modify this thread's state. 1182683Sktlim@umich.edu */ 1192680Sktlim@umich.edu ThreadContext *tc; 1202SN/A 1211858SN/A#if FULL_SYSTEM 1222SN/A Addr dbg_vtophys(Addr addr); 1232SN/A 1242SN/A bool interval_stats; 1252SN/A#endif 1262SN/A 1272SN/A // current instruction 1284181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1294181Sgblack@eecs.umich.edu 1304182Sgblack@eecs.umich.edu // The predecoder 1314182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1322SN/A 1332107SN/A StaticInstPtr curStaticInst; 1343276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1351469SN/A 1364377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1374377Sgblack@eecs.umich.edu Addr fetchOffset; 1384377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1394377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1404377Sgblack@eecs.umich.edu bool stayAtPC; 1414377Sgblack@eecs.umich.edu 1422623SN/A void checkForInterrupts(); 1432662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1442623SN/A void preExecute(); 1452623SN/A void postExecute(); 1462623SN/A void advancePC(Fault fault); 147180SN/A 148393SN/A virtual void deallocateContext(int thread_num); 149393SN/A virtual void haltContext(int thread_num); 1502SN/A 1512SN/A // statistics 152334SN/A virtual void regStats(); 153334SN/A virtual void resetStats(); 1542SN/A 1552SN/A // number of simulated instructions 1562SN/A Counter numInst; 157334SN/A Counter startNumInst; 158729SN/A Stats::Scalar<> numInsts; 159707SN/A 1604998Sgblack@eecs.umich.edu void countInst() 1614998Sgblack@eecs.umich.edu { 1624998Sgblack@eecs.umich.edu numInst++; 1634998Sgblack@eecs.umich.edu numInsts++; 1644998Sgblack@eecs.umich.edu 1654998Sgblack@eecs.umich.edu thread->funcExeInst++; 1664998Sgblack@eecs.umich.edu } 1674998Sgblack@eecs.umich.edu 168707SN/A virtual Counter totalInstructions() const 169707SN/A { 170707SN/A return numInst - startNumInst; 171707SN/A } 1722SN/A 1734564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1744564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1754564Sgblack@eecs.umich.edu 1762SN/A // number of simulated memory references 177729SN/A Stats::Scalar<> numMemRefs; 1782SN/A 179124SN/A // number of simulated loads 180124SN/A Counter numLoad; 181334SN/A Counter startNumLoad; 182124SN/A 1832SN/A // number of idle cycles 184729SN/A Stats::Average<> notIdleFraction; 185729SN/A Stats::Formula idleFraction; 1862SN/A 1872390SN/A // number of cycles stalled for I-cache responses 188729SN/A Stats::Scalar<> icacheStallCycles; 1892SN/A Counter lastIcacheStall; 1902SN/A 1912390SN/A // number of cycles stalled for I-cache retries 1922390SN/A Stats::Scalar<> icacheRetryCycles; 1932390SN/A Counter lastIcacheRetry; 1942390SN/A 1952390SN/A // number of cycles stalled for D-cache responses 196729SN/A Stats::Scalar<> dcacheStallCycles; 1972SN/A Counter lastDcacheStall; 1982SN/A 1992390SN/A // number of cycles stalled for D-cache retries 2002390SN/A Stats::Scalar<> dcacheRetryCycles; 2012390SN/A Counter lastDcacheRetry; 2022390SN/A 203217SN/A virtual void serialize(std::ostream &os); 204237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2052SN/A 2061371SN/A // These functions are only used in CPU models that split 2071371SN/A // effective address computation from the actual memory access. 2082623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2093918Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2103918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2111371SN/A 212581SN/A void prefetch(Addr addr, unsigned flags) 2132SN/A { 2142SN/A // need to do this... 2152SN/A } 2162SN/A 217753SN/A void writeHint(Addr addr, int size, unsigned flags) 2182SN/A { 2192SN/A // need to do this... 2202SN/A } 221594SN/A 2224661Sksewell@umich.edu 223595SN/A Fault copySrcTranslate(Addr src); 224594SN/A 225595SN/A Fault copy(Addr dest); 226705SN/A 227726SN/A // The register accessor methods provide the index of the 228726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 229726SN/A // register index, to simplify the implementation of register 230726SN/A // renaming. We find the architectural register index by indexing 231726SN/A // into the instruction's own operand index table. Note that a 232726SN/A // raw pointer to the StaticInst is provided instead of a 233726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 234726SN/A // long as these methods don't copy the pointer into any long-term 235726SN/A // storage (which is pretty hard to imagine they would have reason 236726SN/A // to do). 237705SN/A 2383735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 239726SN/A { 2402683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 241726SN/A } 242705SN/A 2433735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 244726SN/A { 245726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2462683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 247726SN/A } 248705SN/A 2493735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 250726SN/A { 251726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2522683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 253726SN/A } 254705SN/A 2553735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2563735Sstever@eecs.umich.edu int width) 257726SN/A { 258726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2592683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2602455SN/A } 2612455SN/A 2623735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2632455SN/A { 2642455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2652683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 266726SN/A } 267705SN/A 2683735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 269726SN/A { 2702683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 271726SN/A } 272705SN/A 2733735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2743735Sstever@eecs.umich.edu int width) 275726SN/A { 276726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2772683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 278726SN/A } 279705SN/A 2803735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 281726SN/A { 282726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2832683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 284726SN/A } 285726SN/A 2863735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2873735Sstever@eecs.umich.edu FloatRegBits val, int width) 288726SN/A { 289726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2902683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2912455SN/A } 2922455SN/A 2933735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2943735Sstever@eecs.umich.edu FloatRegBits val) 2952455SN/A { 2962455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2972683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 298726SN/A } 299705SN/A 3002683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 3014950Sgblack@eecs.umich.edu uint64_t readMicroPC() { return thread->readMicroPC(); } 3022683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 3034950Sgblack@eecs.umich.edu uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 3042683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 3052447SN/A 3062683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 3074950Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 3082683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 3094950Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 3102683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 311705SN/A 3124172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3134172Ssaidi@eecs.umich.edu { 3144172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3154172Ssaidi@eecs.umich.edu } 3164172Ssaidi@eecs.umich.edu 3172159SN/A MiscReg readMiscReg(int misc_reg) 3182159SN/A { 3192683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3202159SN/A } 321705SN/A 3224172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3232159SN/A { 3244172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3252159SN/A } 3262159SN/A 3273468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3282159SN/A { 3292683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3302159SN/A } 3312159SN/A 3324185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3332159SN/A { 3344172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3354172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3362159SN/A } 337705SN/A 3384185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3393792Sgblack@eecs.umich.edu { 3403792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3413792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3423792Sgblack@eecs.umich.edu } 3433792Sgblack@eecs.umich.edu 3444185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3453792Sgblack@eecs.umich.edu { 3463792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3474172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3483792Sgblack@eecs.umich.edu } 3493792Sgblack@eecs.umich.edu 3504185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3513792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3523792Sgblack@eecs.umich.edu { 3533792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3544172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3553792Sgblack@eecs.umich.edu } 3563792Sgblack@eecs.umich.edu 3574027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3584027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3594027Sstever@eecs.umich.edu } 3604027Sstever@eecs.umich.edu 3614027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3624027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3634027Sstever@eecs.umich.edu } 3644027Sstever@eecs.umich.edu 3654661Sksewell@umich.edu MiscReg readRegOtherThread(int regIdx, int tid = -1) 3664661Sksewell@umich.edu { 3674661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3684661Sksewell@umich.edu "register access.\n"); 3694661Sksewell@umich.edu } 3704661Sksewell@umich.edu 3714661Sksewell@umich.edu void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1) 3724661Sksewell@umich.edu { 3734661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3744661Sksewell@umich.edu "register access.\n"); 3754661Sksewell@umich.edu } 3764661Sksewell@umich.edu 3771858SN/A#if FULL_SYSTEM 3782683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3792680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3802683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 381705SN/A#else 3822683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 383705SN/A#endif 384705SN/A 3852683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3862680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3872SN/A}; 3882SN/A 3892623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 390