atomic.hh revision 9342 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "cpu/simple/base.hh"
47#include "params/AtomicSimpleCPU.hh"
48
49class AtomicSimpleCPU : public BaseSimpleCPU
50{
51  public:
52
53    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
54    virtual ~AtomicSimpleCPU();
55
56    virtual void init();
57
58  private:
59
60    struct TickEvent : public Event
61    {
62        AtomicSimpleCPU *cpu;
63
64        TickEvent(AtomicSimpleCPU *c);
65        void process();
66        const char *description() const;
67    };
68
69    TickEvent tickEvent;
70
71    const int width;
72    bool locked;
73    const bool simulate_data_stalls;
74    const bool simulate_inst_stalls;
75
76    // main simulation loop (one cycle)
77    void tick();
78
79    /**
80     * An AtomicCPUPort overrides the default behaviour of the
81     * recvAtomic and ignores the packet instead of panicking.
82     */
83    class AtomicCPUPort : public CpuPort
84    {
85
86      public:
87
88        AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
89            : CpuPort(_name, _cpu)
90        { }
91
92      protected:
93
94        virtual Tick recvAtomicSnoop(PacketPtr pkt)
95        {
96            // Snooping a coherence request, just return
97            return 0;
98        }
99
100    };
101
102    AtomicCPUPort icachePort;
103    AtomicCPUPort dcachePort;
104
105    bool fastmem;
106    Request ifetch_req;
107    Request data_read_req;
108    Request data_write_req;
109
110    bool dcache_access;
111    Tick dcache_latency;
112
113  protected:
114
115    /** Return a reference to the data port. */
116    virtual CpuPort &getDataPort() { return dcachePort; }
117
118    /** Return a reference to the instruction port. */
119    virtual CpuPort &getInstPort() { return icachePort; }
120
121  public:
122
123    virtual void serialize(std::ostream &os);
124    virtual void unserialize(Checkpoint *cp, const std::string &section);
125
126    unsigned int drain(DrainManager *drain_manager);
127    void drainResume();
128
129    void switchOut();
130    void takeOverFrom(BaseCPU *oldCPU);
131
132    virtual void activateContext(ThreadID thread_num, Cycles delay);
133    virtual void suspendContext(ThreadID thread_num);
134
135    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
136
137    Fault writeMem(uint8_t *data, unsigned size,
138                   Addr addr, unsigned flags, uint64_t *res);
139
140    /**
141     * Print state of address in memory system via PrintReq (for
142     * debugging).
143     */
144    void printAddr(Addr a);
145};
146
147#endif // __CPU_SIMPLE_ATOMIC_HH__
148