atomic.hh revision 4870:fcc39d001154
1360SN/A/* 21458SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu */ 30360SN/A 31360SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 322093SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 33360SN/A 34360SN/A#include "cpu/simple/base.hh" 35360SN/A 36360SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 37360SN/A{ 38360SN/A public: 392474SN/A 40360SN/A struct Params : public BaseSimpleCPU::Params { 412680Sktlim@umich.edu int width; 421717SN/A bool simulate_stalls; 432474SN/A }; 44360SN/A 456029Ssteve.reinhardt@amd.com AtomicSimpleCPU(Params *params); 46360SN/A virtual ~AtomicSimpleCPU(); 472667Sstever@eecs.umich.edu 48360SN/A virtual void init(); 49360SN/A 502107SN/A public: 51360SN/A // 52360SN/A enum Status { 533114Sgblack@eecs.umich.edu Running, 54360SN/A Idle, 552495SN/A SwitchedOut 562680Sktlim@umich.edu }; 575958Sgblack@eecs.umich.edu 585958Sgblack@eecs.umich.edu protected: 59360SN/A Status _status; 602680Sktlim@umich.edu 61360SN/A Status status() const { return _status; } 622495SN/A 632680Sktlim@umich.edu private: 64360SN/A 651450SN/A struct TickEvent : public Event 665958Sgblack@eecs.umich.edu { 67360SN/A AtomicSimpleCPU *cpu; 68360SN/A 69360SN/A TickEvent(AtomicSimpleCPU *c); 701450SN/A void process(); 713114Sgblack@eecs.umich.edu const char *description(); 722680Sktlim@umich.edu }; 73360SN/A 741969SN/A TickEvent tickEvent; 752484SN/A 762484SN/A const int width; 77360SN/A const bool simulate_stalls; 78360SN/A 79360SN/A // main simulation loop (one cycle) 801450SN/A void tick(); 813114Sgblack@eecs.umich.edu 822680Sktlim@umich.edu class CpuPort : public Port 83360SN/A { 841969SN/A public: 855958Sgblack@eecs.umich.edu 86360SN/A CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 871458SN/A : Port(_name, _cpu), cpu(_cpu) 88360SN/A { } 89360SN/A 90360SN/A bool snoopRangeSent; 911450SN/A 923114Sgblack@eecs.umich.edu protected: 932680Sktlim@umich.edu 94360SN/A AtomicSimpleCPU *cpu; 956029Ssteve.reinhardt@amd.com 966029Ssteve.reinhardt@amd.com virtual bool recvTiming(PacketPtr pkt); 975958Sgblack@eecs.umich.edu 986029Ssteve.reinhardt@amd.com virtual Tick recvAtomic(PacketPtr pkt); 996029Ssteve.reinhardt@amd.com 1006029Ssteve.reinhardt@amd.com virtual void recvFunctional(PacketPtr pkt); 1016029Ssteve.reinhardt@amd.com 1022834Sksewell@umich.edu virtual void recvStatusChange(Status status); 103360SN/A 1041458SN/A virtual void recvRetry(); 105360SN/A 106360SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 107360SN/A bool &snoop) 1081450SN/A { resp.clear(); snoop = true; } 1096109Ssanchezd@stanford.edu 1106109Ssanchezd@stanford.edu }; 1116109Ssanchezd@stanford.edu CpuPort icachePort; 1126109Ssanchezd@stanford.edu 1136109Ssanchezd@stanford.edu class DcachePort : public CpuPort 1146109Ssanchezd@stanford.edu { 1156109Ssanchezd@stanford.edu public: 1166109Ssanchezd@stanford.edu DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu) 1176109Ssanchezd@stanford.edu : CpuPort(_name, _cpu) 1186109Ssanchezd@stanford.edu { } 1196109Ssanchezd@stanford.edu 1206109Ssanchezd@stanford.edu virtual void setPeer(Port *port); 1216109Ssanchezd@stanford.edu }; 1223114Sgblack@eecs.umich.edu DcachePort dcachePort; 123360SN/A 1242107SN/A Request ifetch_req; 125360SN/A Request data_read_req; 126360SN/A Request data_write_req; 127360SN/A 1281450SN/A bool dcache_access; 1295748SSteve.Reinhardt@amd.com Tick dcache_latency; 130360SN/A 131360SN/A public: 1325958Sgblack@eecs.umich.edu 1335748SSteve.Reinhardt@amd.com virtual Port *getPort(const std::string &if_name, int idx = -1); 1345748SSteve.Reinhardt@amd.com 1355748SSteve.Reinhardt@amd.com virtual void serialize(std::ostream &os); 1365748SSteve.Reinhardt@amd.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1375748SSteve.Reinhardt@amd.com virtual void resume(); 1385748SSteve.Reinhardt@amd.com 1395748SSteve.Reinhardt@amd.com void switchOut(); 1405748SSteve.Reinhardt@amd.com void takeOverFrom(BaseCPU *oldCPU); 1412474SN/A 1422474SN/A virtual void activateContext(int thread_num, int delay); 1435748SSteve.Reinhardt@amd.com virtual void suspendContext(int thread_num); 1442474SN/A 1452474SN/A template <class T> 1462474SN/A Fault read(Addr addr, T &data, unsigned flags); 1471450SN/A 1485748SSteve.Reinhardt@amd.com template <class T> 1495748SSteve.Reinhardt@amd.com Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1501458SN/A}; 1511458SN/A 152360SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 153360SN/A