atomic.hh revision 4475:fb185cc1c845 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35
36class AtomicSimpleCPU : public BaseSimpleCPU
37{
38  public:
39
40    struct Params : public BaseSimpleCPU::Params {
41        int width;
42        bool simulate_stalls;
43    };
44
45    AtomicSimpleCPU(Params *params);
46    virtual ~AtomicSimpleCPU();
47
48    virtual void init();
49
50  public:
51    //
52    enum Status {
53        Running,
54        Idle,
55        SwitchedOut
56    };
57
58  protected:
59    Status _status;
60
61    Status status() const { return _status; }
62
63  private:
64
65    struct TickEvent : public Event
66    {
67        AtomicSimpleCPU *cpu;
68
69        TickEvent(AtomicSimpleCPU *c);
70        void process();
71        const char *description();
72    };
73
74    TickEvent tickEvent;
75
76    const int width;
77    const bool simulate_stalls;
78
79    // main simulation loop (one cycle)
80    void tick();
81
82    class CpuPort : public Port
83    {
84      public:
85
86        CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
87            : Port(_name, _cpu), cpu(_cpu)
88        { }
89
90        bool snoopRangeSent;
91
92      protected:
93
94        AtomicSimpleCPU *cpu;
95
96        virtual bool recvTiming(PacketPtr pkt);
97
98        virtual Tick recvAtomic(PacketPtr pkt);
99
100        virtual void recvFunctional(PacketPtr pkt);
101
102        virtual void recvStatusChange(Status status);
103
104        virtual void recvRetry();
105
106        virtual void getDeviceAddressRanges(AddrRangeList &resp,
107            bool &snoop)
108        { resp.clear(); snoop = true; }
109
110    };
111    CpuPort icachePort;
112
113    class DcachePort : public CpuPort
114    {
115      public:
116        DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
117            : CpuPort(_name, _cpu)
118        { }
119
120        virtual void setPeer(Port *port);
121    };
122    DcachePort dcachePort;
123
124    Request  *ifetch_req;
125    PacketPtr ifetch_pkt;
126    Request  *data_read_req;
127    PacketPtr data_read_pkt;
128    Request  *data_write_req;
129    PacketPtr data_write_pkt;
130    PacketPtr data_swap_pkt;
131
132    bool dcache_access;
133    Tick dcache_latency;
134
135  public:
136
137    virtual Port *getPort(const std::string &if_name, int idx = -1);
138
139    virtual void serialize(std::ostream &os);
140    virtual void unserialize(Checkpoint *cp, const std::string &section);
141    virtual void resume();
142
143    void switchOut();
144    void takeOverFrom(BaseCPU *oldCPU);
145
146    virtual void activateContext(int thread_num, int delay);
147    virtual void suspendContext(int thread_num);
148
149    template <class T>
150    Fault read(Addr addr, T &data, unsigned flags);
151
152    template <class T>
153    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
154};
155
156#endif // __CPU_SIMPLE_ATOMIC_HH__
157